Researchers from the University of Lancaster in the UK have succeeded in their efforts to create a type of non-volatile flash memory that is as fast as DRAM but uses just 1% of the energy that modern-day NAND or DRAM memory needs to write bits of data. The memory is called UK III-V Memory, as reported by ElectronicsWeekly.
The power usage required is about 10 to the power of -17 Joules for a gate built on the 20nm lithographic process. The UK III-V memory's transistors will have a typically-off state, and charging a gate would take about 5ns with depletion taking 3ns, both of which are very respectable figures. It's likely that once in a product through a controller these figures would be a tad higher, but that would be a worthwhile trade-off for the gained efficiency.
The development is still in the stage of single transistors, so translating this to a fully-fledged commercial product is still a long ways away. Nevertheless, the achievement to build non-volatile memory that is this efficient and fast enough to compete with DRAM is quite the achievement.
“The channel exploits the unusual [type-III] band alignment of In(Ga)As and GaSb, where the conduction band of InAs is below the valence band of GaSb," lead researching Professor Manus Hayne told Electronics Weekly.
"This means that even in the absence of doping electrons will flow from the full valence band of the GaSb into the conduction band of the InAs channel. This was the case before, but here we have made the In(Ga)As channel narrow so that confinement pushes the energy of the channel state up to just above the GaSb valence band, such that it is unoccupied and normally-off, unless a suitable voltage is applied. This allows a readout that is similar to flash and should deliver far superior 1-0 contrast to our previous devices allowing them to be connected in a fully-addressable array."
Having non-volatile memory as fast as DRAM is interesting because it can be used to build PCs that can maintain the data we currently keep in RAM when the system is fully switched off and can, therefore, resume in an instant from where you left off from a full-off state. This would eliminate the need for sleep states and also allow systems to power down the RAM when they are idling, further reducing power consumption.
The question that comes to mind is whether the UK III-V memory can handle the repeated re-writes to DRAM is typically subjected. If wear is an issue, that could crush any dreams of a computer with non-volatile RAM.
