The x86 Ecosystem Advisory Group turns one year old.
(Image credit: Intel)
AMD and Intel are celebrating one year since the formation of the x86 Ecosystem Advisory Group, an alliance designed to coordinate the evolution of the x86 instruction set architecture (ISA) and ensure that new features are supported by both leading CPU designers. In the first year, AMD and Intel have managed to ratify four new features that are set to be supported by the upcoming processors from these companies, including long-awaited memory tagging.
The new cross-vendor capabilities agreed upon by AMD and Intel are ACE (Advanced Matrix Extension) and AVX10 to enhance the performance of matrix multiplication and vector operations, as well as FRED (Flexible Return and Event Delivery) and ChkTag (x86 Memory Tagging) to reduce latency between software and hardware, as well as to detect errors like buffer overflows or use-after free bugs.
Intel's Granite Rapids processors already support AVX10.1 and AMX, whereas Sapphire Rapids were first to support AMX instructions. With the ratification by the x86 EDA, AVX10 and AMX will be supported by AMD's next-generation processors, though we can only wonder whether this will happen with Zen 6 or already with Zen 7. Other capabilities are less well-known.
Intel introduced FRED publicly in 2023, and by now, the capability is well-documented in developer documentation. The technology is described as a replacement for traditional x86 interrupt and exception mechanisms, so ultimately it is designed to simplify context switches, reduce latency, improve performance, and security when working with operating systems that support it.
FRED speeds up how the CPU switches between user mode (ring 3) and kernel mode (ring 0) with a hardware-defined entry and exit path. While this does not sound too impressive, replacing the old x86 mechanism (which uses the Interrupt Descriptor Table and IRET) is a big deal. At present, every time an application interacts with the OS (which happens millions of times per second), the CPU must switch between user mode and kernel mode, which introduces fairly high latencies with today's machines. Since the traditional IDT and IRET mechanisms are software-managed, while FRED provides a hardware-defined and verified entry and return path, replacing the former with the latter also improves reliability and security, in addition to performance
Up until today, AMD's stance on FRED was unclear, but now that the feature is recognized by the x86 EAG as a cross-vendor capability, it will be added to AMD's platforms over time.
Perhaps the most interesting addition to the list of cross-vendor x86 EAG features is the ChkTag (x86 Memory Tagging) capability, which has not been widely discussed before. The feature is added to catch memory safety errors — problems like buffer overflows, use-after-free, and out-of-bounds memory access — directly in hardware. Memory tagging is rapidly becoming a standard feature in modern CPUs as it is valuable (can catch a variety of bugs in hardware) and easy to implement, which is why modern processors from Apple and Ampere now support Arm's MTE technology.
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It is hard to say when AMD and Intel plan to implement ChkTag (x86 Memory Tagging) in their processors. The announcement by the x86 Ecosystem Advisory Group signals both are committed to supporting this feature, but there is no obligation to implement it within a certain timeframe. Meanwhile, hardware changes of this depth typically require building them into the CPU microarchitecture itself, so expect support of FRED and ChkTag to come several years down the road.
Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
The new cross-vendor capabilities agreed upon by AMD and Intel are ...
APX is conspicuous in its absence. It seems already baked into upcoming Intel cores (Nova Lake, Diamond Rapids?). I hope it doesn't get fused off, for lack of an agreed standard!
The article said:
With the ratification by the x86 EDA, AVX10 and AMX will be supported by AMD's next-generation processors, though we can only wonder whether this will happen with Zen 6 or already with Zen 7. Other capabilities are less well-known.
Well, AVX10.1 should be trivial to implement, if you've already got a fairly complete AVX-512 implementation (as AMD does). So, I'd be surprised if it's not included in Zen 6.
AMX is another can of worms, entirely. It adds a lot of bloat to each core, since it adds 8 kB of ISA register state and requires a "sea of MACs" for a worthwhile implementation. I don't foresee either Intel or AMD putting it in all of their client cores any time soon. That still leaves open the question of whether to put it in CCD chiplets, so long as AMD continues to share them between client & server, but I'd bet it's not happening for Zen 6, at the very least.
There's a lot else they seem not to have unified on, such as the memory encryption extensions they each developed and AMD's INVLPGB, which does remote shoot-downs of pages in other cores' TLBs. It's good to see standardization on FRED, at least.
if you've already got a fairly complete AVX-512 implementation (as AMD does). So, I'd be surprised if it's not included in Zen 6.
Have you really seen any improvement with it more than few percents? Ian Cutress 5x speedups with AVX512 look like a hoax "Some engineer at Intel who then left Intel improved my code with AVX512, I do not know how and what he has done there..."
