AMD's memory patent outlining a 'new, improved RAM' made from DDR5 memory isn't a new development — HB-DIMMs already superseded, probably won't come to market

A 256-gigabyte Micron MCRDIMM in tall form factor.
(Image credit: Tom's Hardware)

A recent AMD patent, US19/201,497 titled "High-bandwidth memory module architecture," is making the rounds again, with posts like this one on Reddit prompting all kinds of speculation about the "new" HB-DIMM memory technology that AMD is preparing. However, AMD is probably not preparing anything new; Instead, the new patent is actually a continuation of an older one that dates to 2022. The technology the company outlines has already been superseded by the new MRDIMM tech that's already shipping and supported by AMD. 

The original patent, known as US12300346B2 and also titled "High-bandwidth memory module architecture," was superseded in 2023 by US20230178121A1, which is the specific document extended by the "new" filing that was actually published back in July. In other words, by no means is this a novel technology, and AMD's recent activity with these patents is almost assuredly a form of "bureaucratic housekeeping" — paper shuffling intended to help protect AMD's intellectual property.

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Zak Killian
Contributor

Zak is a freelance contributor to Tom's Hardware with decades of PC benchmarking experience who has also written for HotHardware and The Tech Report. A modern-day Renaissance man, he may not be an expert on anything, but he knows just a little about nearly everything.

  • bit_user
    The article said:
    Multiple companies independently developed this idea; SK hynix pursued it in collaboration with Intel and Renesas, presenting a proposal called MCR-DIMM in late 2022. That was after AMD had already filed its patent on HB-DIMM, although the filing wasn't public at that time. It wouldn't do to have two competing, incompatible standards, so JEDEC got together with the two to standardize what we now have as MRDIMMs, or Multiplexed-Rank Dual Inline Memory Modules. MRDIMMs consolidate the ideas of MCR-DIMM and HB-DIMM into one standard form.
    I thought that Intel's "MR" DIMMs were basically MCR-DIMMs and that they did an end-run around the JEDEC standardization process for MR-DIMMs.

    The article said:
    Phoronix recently tested the performance gains against standard DDR5 RDIMMs at 6400 Mbps and while the overall gains were small
    The GeoMean improved by 8.3%, which is not something I think most datacenter operators would consider small. I think < ~2% would be small.

    However, power consumption increased 15.1%. So, if you tweaked turbo and power limits to run at about equal power, then I'd bet the performance gains might indeed drop to the 2% ballpark.

    Something else to note about Phoronix' tests is that he runs one instance of the program, unless it's something like compiling, which is fundamentally multi-process. So, he does a better job in characterizing developer or HPC workloads, but misses a lot of datacenter scenarios that involve lots of VMs. In the many-VM scenarios, you basically have bunches of independent workloads and kernels, which scales much more linearly and might benefit even more from additional memory bandwidth.

    The article said:
    So, in summary: No, AMD (probably) isn't about to whip out some new high-speed memory technology. This stuff has been talked about for a few years already,
    Yeah, MR-DIMMs were discussed over the past years and Intel's aggressive adoption of similar tech gave Granite Rapids one axis on which it surpassed the Turin (Zen 5) EPYCs. So, it was abundantly clear AMD would have to answer Intel by doing similar.

    Incidentally, I think the move to 16 channels is probably as much about capacity as it is about bandwidth. I fully expect they'll be dropping 2DPC as something they even nominally support, in the next generation of EPYCs. Without that, the only way to add more capacity is by adding more channels (or more DRAM per DIMM).

    And on the client front, I fully expect Zen 6 to offer native support for CU-DIMM. In moving up to a maximum spec of 24 cores per CPU (2x 12-core CCDs), they'll sure need a jump in bandwidth. AMD has previously claimed bandwidth constraints were the main reason why Ryzen hasn't gone above 16 cores. I can dig up a citation on this, if anyone really wants it.
    Reply
  • fredst
    "rumors about AMD's new chiplet APUs are true."

    What rumors? Link please 🥺
    Reply