Samsung puts 3D DRAM on the roadmap, stacked DRAM to follow

DRAM featuring 3D transistors has been discussed for years, but actual makers of memory have refrained from making any real announcements on the matter. However, Samsung decided to break the silence at Memcom last week and revealed some of its plans concerning 3D DRAM. As it turns out, the first 3D DRAM node is just a few years away. 

The world's largest maker of memory plans to adopt DRAM with vertical channel transistors (VCT) starting from its 1st Generation sub-10nm process technology — if the slide that Samsung demonstrated at Memcom reflects the company's actual roadmap (and judging by the company's 10nm-class nodes, it does). The slide has been published by SemiEngineering and was republished by Fred Chen, a technology investigator.  

A vertical channel transistor (VCT) can be a type of FinFET, in which the conducting channel is wrapped by a thin silicon 'fin,' forming the body of the device. A VCT could also be a gate-all-around (GAA) transistor, in which the gate material surrounds the conducting channel from all sides. Based on the image from the slide, we are dealing with a FinFET-based DRAM process technology. 

That 1st Generation sub-10nm DRAM fabrication process is two generations away, as Samsung's latest DRAM production node is its 5th Generation 10nm-class (12nm) technology introduced in mid-2023. Based on the slide, Samsung preps two more 10nm-class production nodes, and the 1st Gen sub-10nm node is set to appear in the second half of the decade. 

Normally, the adoption of 3D transistors for DRAM is associated with achieving a 4F^2 cell design, considered one of the most efficient memory cell layouts ever in terms of manufacturing costs. Tokyo Electron, a leading maker of wafer fab tools, expects DRAMs featuring VCTs and 4F^2 cell design to start emerging in 2027 – 2028. The company believes that to make VCT-based DRAMs; memory makers will have to adopt new materials for capacitors and bitlines. 

Interestingly, Samsung plans to adopt a stacked DRAM process technology sometime in the early 2030s, enabling the company to tangibly increase the density of its memory devices in about ten years. At this point, we can only wonder what densities we'll be looking at in the next decade — though it's likely that we'll be dealing with next-generation DRAM technologies (e.g., DDR6).