Skip to main content

Intel's X25-M Solid State Drive Reviewed

Inside the X25-M SSD: 10-Channel Flash

Why Is the X25-M So Fast?

The question is a good one: how the heck did Intel manage to create a MLC flash SSD that is faster than a high-end SLC product? And why do the drives store 80 GB or 160 GB, while silicon-based chips typically have capacities of 32, 64 and 128 GB? The answer is multi-channel flash. Intel uses its own SATA/300 controller and addresses ten different MLC flash channels at once, using a 16 MB cache memory. It also employs native command queuing (NCQ) to be able to distribute read and write operations across the available channels efficiently. Looking at the printed circuit board you’ll realize that the bottom carries the controller and the cache memory together with five of the ten memory channels (two flash chips each). The top side holds the other ten chips.

The current generation of 50 nm NAND flash stores 32 Gbit (4 GB) per chip. If you now use 20 of them (two per channel times 10 channels) you’ll reach exactly 80 GB. If you distribute reads and write across 10 channels it is obvious that performance will scale beautifully. However, we’re curious about how Intel implements the 80 GB (or 160 GB later on) on the 1.8” form factor, as 20 flash chips plus controller plus DRAM doesn’t fit into the 1.8” envelope (although the double-sided printed circuit board does). Intel will have to work with a smaller number of higher density flash chips, but we can only speculate about the layout. The specification of “up to” 250 MB read and 70 MB/s write performance indicates that not all models might perform alike.

The on-board 16 MB DRAM chip by Samsung is a part that we’ve also seen on various conventional hard drives, which we found somewhat amusing. This is the first flash SSD to implement NCQ, as it typically doesn’t make too much sense on a drive that allows direct access anyway. However, the DRAM buffer is not there to increase performance or to service NCQ for performance reasons. Rather, it is necessary to support write amplification control, which essentially is Intel’s attempt to improve performance while increasing life expectancy.