Inside the X25-M Controller: Wear Leveling, Write Amplification Control
Intel’s X25 product presentations talk a lot about how to estimate the life expectancy of flash memory by calculating so-called NAND cycles: fewer cycles performed for a specific workload means a longer life expectancy. It is desirable to have the flash controller manage write operations efficiently, applying wear leveling algorithms and considering the NAND block size to optimize write operations, which can further reduce the number of actual writes. It is important to consider the usage model (mainstream desktop) as well as the data written (how, how often and how much a system writes to the system drive) to find an ideal way of handling writes.
NAND flash write operations mainly depend on the given block size of the flash memory. This explains why writes wear down NAND flash over time. As a simple example, writing 4 KB of data to a conventional flash drive results in the controller triggering a write at the minimum block size, which can be as much as 128 KB today. This means that all cells storing the 128 KB data block are written, even though only 4 KB of them are actual data. This is called write amplification, and in this example it is 32 for 128 KB written for an effective 4 KB of data.
Cache Needed for Write Amplification Control
This is why Intel’s controller needs the DRAM buffer. It is used as a short term memory to store data, so it can execute write operations more efficiently than a conventional Flash controller, which typically triggers writes one by one, writing huge cells even if the smallest data chunks need to be stored. That’s why MLC-based NAND flash typically has poor random write performance.
Better By Design
Intel uses factors for write amplification and wear leveling to calculate NAND flash cycles in a simple equation. The factor for wear leveling tells you the usage difference between average wear and maximum wear, which Intel specifies as 3 (3x) for other products and only 1.1x for the X25-M as a result of the controller operating with command queuing being aware of the flash memory’s block size. This means that almost all cells are almost evenly utilized, which is great for long life expectancy of the drive.
We already explained two paragraphs above how the factor for write amplification can be calculated. In the example it’s 32, but Intel uses a factor of 20 for its comparison with competitors (check out the image), and as little as 1.1 for its own X25-M drive. The capacity used in the equation equals the typical data written per day (20 GB of data in this example) over five years. Intel rounded up the 36.5 TB result to 40. If you look at the results, you’ll understand Intel’s statement about drastically improved wear, while these features certainly also help to avoid random writes and to maximize performance.