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Memory Timings

Inside were two Mushkin XP2-6400 2 GB modules

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Header Cell - Column 0 Memory TimingABSiBuyPowerFalcon-NWBiohazzardExplanation of the Timing
tCLCAS Latency5545Delay between the CAS signal and the availability of valid data on the data pins (DQ)
tRCDRAS to CAS Delay6544Dealy before a read/write command after bank activativation. The cells need to be stabilized by sense amplifiers for proper operation.
tRPRAS Precharge (Row to Row)6544Time delay needed to close one row access and open a new one
tRASRAS Active to Precharge Delay18181514Minimum RAS activation time delay or the time from the bank activate command until the precharge command an be executed.
CMDChip Select Issue Delay (Command Rate)2222Time needed between the chip select signal and when commands can be issued to the RAM module IC.
tRRDRas to RAS Delay (Between Banks)N/A345Row to Row delay from one bank to one on another active bank
tRCRas to RAS Delay - Bank Cycle Time (Same Bank)21221334Row to Row delay on the same bank. One row discharges and another is activated. (Minimum time of tRAS = tRP)
tWRWrite Recovery TimeN/A546Delay between writes to ensure a proper writing to the cells. Ideally tRAS minus tRCD to ensure a premature RAS precharge does not wipe out the data.
tWTRWrite to Read DelayN/A9911The delay to prep the bus for read after a write. (Turn on or off the appropriate I/O buffers, clear existing data, etc.)
tREFDRAM Auto-Refresh RateN/A7.87.87.8Rate at with the DRAM's charge is refreshed in micro seconds. Prevents corruption by sending data to sense amplifiers and back to the refreshed cell.