Overclocking And Under-Latency Results
CAS latency is measured in cycles, but cycle times get shorter as frequency is increased. As an example, DDR3-2666 CAS 16 would have the same latency in real-time as DDR3-1333 CAS 8.
Real-time latency improvement has lagged behind frequency improvement for as long as most of us can remember, and Team Group's Xtreem modules push this setting to the 15-cycle limits of some motherboards with the programmed 11-15-15-31 timings of its DDR3-2800. We used its timings as the limit for our overclocking attempts.
Surprisingly, G.Skill’s DDR3-2133 kit overclocked better than Team Group’s DDR3-2800 on this platform. Intel-optimized timings could bear part of the blame, but we did request that each manufacturer send its most AMD-optimized overclocking memory product, knowing ahead of time the platform we'd be using.
Our DDR3-1600 baseline remains at stock speed, showing how much further these overclocking-optimized modules can push the processor’s memory controller.
Of course, CAS 11-15-15-31 isn’t really needed at the motherboard’s top memory ratio. We went on to test how quickly each of these module sets could run at data rates from 1600 to 2400 MT/s.
| Best Timings at 1.65 V | ||||
|---|---|---|---|---|
| Row 0 - Cell 0 | DDR3-2400 | DDR3-2133 | DDR3-1866 | DDR3-1600 |
| Team Group Xtreem LV TXD38192M2800HC11RDC-L | 9-12-11-24 | 8-10-10-24 | 7-9-8-24 | 6-8-7-21 |
| G.Skill Ripjaws X F3-17000CL9D-8GBXM | 10-12-11-24 | 9-11-10-24 | 8-10-9-24 | 7-9-8-24 |
| Super Talent Quadra WQ213UX16G | Unstable | 9-12-10-28 | 8-10-9-25 | 7-9-8-22 |
| Kingston HyperX KHX2400C11D3K4/8GX | Unstable | 10-12-10-30 | 8-10-9-25 | 7-9-8-22 |
| Reference DDR3-1600 C9 8GB Dual Channel | Row 5 - Cell 1 | Row 5 - Cell 2 | Row 5 - Cell 3 | 9-9-9-28 |
Proving that it didn't send us a one-trick pony, Team Group’s top-rated DDR3-2800 also tops all of our latency tests.
Note that tRAS appears unrealistically long for all of our tests. That’s because we set it to its best performing setting. Whilst some of these modules could operate stable at half the shown tRAS, any tRAS setting outside of the 21-24 cycle range would cause a stumble in Sandra's Memory Bandwidth benchmark module. This appears to be AMD-specific, since we’ve achieved higher performance at far lower tRAS on several Intel processors.
