Gigabit Ethernet: On-Board Chips Reviewed

The Overview

Option 1: The network chip is connected via the PCI bus. This is simple and cost-efficient.

At first sight, integrating a network controller through a connection to the PCI Bus (Peripheral Components Interconnect, Illustration 1) makes sense. Still, in everyday real-life operations, that brings about a small disadvantage - especially when several PCI devices are used simultaneously: As the PCI represents a parallel bus system, all existing devices have to share its bus bandwidth of 133 MB/s. And during simultaneous activity of several "demanding" PCI devices, bottlenecks can emerge quickly.

As a result, many mobo makers have begun detaching the network controller from the PCI Bus. Since chipset makers have been pursuing this approach for many product generations now, even the simplest system sports a 100 MBit interface, which is fully sufficient for most desktop applications (Illustration 2).

When connecting a Gigabit Ethernet chip, there is a lot of data traffic between the Northbridge and the Southbridge. That's why manufacturers are trying to shorten the unnecessary routes of network data. Intel led the way here by adding a new interface to the 765/875 components called CSA (Communications Streaming Architecture). It offers a bandwidth of 2 GBit/s or 266 MBit/s - just as much as Gigabit Ethernet during full-duplex operations.

An integrated network chip cuts build costs and takes some load off the PCI Bus. However, in early models, the load on the processor is greater. However, due to the performance available today, this negative factor is of little relevance for 100 MBit Ethernet.

The status quo at Intel: A Gigabit chip should be connected via CSA. In contrast to the PCI Bus, it always offers the complete bandwidth and does not always "drag" the network data through the bus that is serving Northbridge and Southbridge.