Today Vs. Tomorrow
The heavily loaded point-to-point interconnect with three end points will be replaced by Bensley's DIB design (Dual Independent Bus), finally attaching each processor with a separate Front Side Bus. Speeds will extend to 266 MHz (FSB1066), boosting the bandwidth up to 8.5 GB/s per processor.
At the same time, the memory controller is beefed up to not only support DDR2-400 dual channel operation, but DDR2-533 at quad-channel mode. Again, the total gross bandwidth increases from 6.4 GB/s to approximately 17 GB/s.
Although these changes look rather promising it remains to be seen how well they translate into real-life performance gains. It is especially difficult to estimate the efficiency of the quad-channel memory controller at this point. Having seen some early systems we would tend to say that the dual independent bus is the most important factor for speeding up the Xeon architecture.
Fully Buffered DImms Are The Achilles Heel
Indeed, we found the memory question to be a real problem. Not only are the buffer chips of FB-DIM modules running hotter than Intel expected, but we can also see customers wondering why they should yet again change their memory technology.
Lindenhurst introduced registered DDR2-400 memory with ECC, which in fact does not really provide more performance than DDR333. Yet lots of systems were shipped with DDR2 memory. However, systems that required vast amounts of memory would have to go to lower speed DDR memory anyway - leaving very little to justify DDR2.
Although FB-DIMM is definitely going to be the standard for quite some time, it remains questionable for us whether the market will be ready to go FB-DIMM when Intel is.
