Summary Of 3D Architecture
- 0.13µ process
- Flip-chip design
- 256-bit GPU
- 125 million transistors
- 8 pixel shaders
- Vertex shader array
- AGP 8X
- Max. power input 75W, auxilliary power supply
- Geometry: more than 90 million triangles per second
- 16x FSAA
- Genlock / framelock
- 6 freely definable hardware user clip planes
- IEEE 128 bit floating point (FP) frame buffer
- 32 bits per component
- Optional speed mode with 16-bit FP
- 16 textures per pixel
- Single-pass volume rendering
Memory Architecture
NVIDIA is breaking new ground by establishing DDR2 memory for graphics cards. DDR (double data rate) already transfers the data at the rising and falling edge of the clock. However, DDR2 does not mean that four transfers per clock are executed. The increase in bandwidth over the old single data rate memory is in part due to the two transfers per speed (rising and falling edge) and in part due to the doubling of the bursts from two to four. The bursts are handled internally in the chip, however, and not during transfer.
The memory bandwidth of 19.8 GBytes per second for the Radeon 9700 Pro is clearly higher than for the QuadroFX 2000, which only produces 12.8 GBytes per second. Thus, DDR2 isn't the be-all and end-all in the memory system. Far more important is the memory bus width. With ATi (conventional DDR memory) that's 256 bits. NVIDIA, on the other hand, allows just 128 bits, despite DDR2.
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To compensate for the obvious disadvantage in memory bandwidth, NVIDIA has equipped the chip - which already comes with Z compression - with color compression as well. This allows lossless compression of color data with a factor of up to 4:1 in real time. NVIDIA claims that compressing color data enhances efficiency considerably since all color data can be perfectly compressed right up to the edges of polygons.
Summary Of Memory Architecture
- Lossless 4:1 color compression
- Lossless Z compression
- 128-bit memory bus with DDR2 memory
Compared with its predecessors (NV25 and NV28), the pixel and vertex shader has grown considerably in complexity. Now, loops can be run from within shader programs. To simplify shader programming, NVIDIA invested in the Cg development environment. This compiler is based on the powerful programming language C++, yet is also highly compatible with Microsoft's High Level Shader Language (HLSL).
Although C++ is an all-around programming language, it has the decisive disadvantage that programs for 3D hardware have to be written directly. Cg, on the other hand, delivers ready-to-use models and libraries and can be used across a range of platforms. Thus, the programmer doesn't necessarily need to understand the 3D hardware in detail, but can concentrate on the actual solution. This translates into dramatic reductions in development time for OpenGL applications for real-time shaders and visual effects.
