AM5 Socket May Be AMD's Doorway To DDR5

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Hardware leaker ExecutableFix, who has a good track record, has shared the potential specifications for AMD's forthcoming AM5 socket. Nonetheless, this is the first time that we've seen anything related to AM5 so take the information with a bit of salt.

The Twitter user started his tweet with mentions of the LGA1718 socket. This is the most interesting bit since AMD has been using a Pin Grid Array (PGA) design for its mainstream chips for over a decade now. If the leaker's information is accurate, the AM5 socket might finally switch over to a Land Grid Array (LGA), just like Intel.

The current AM4 socket has a total of 1,331 contacts. The AM5 socket, on the other hand, reportedly arrives with 1,718 contacts. It's a pretty significant 29.1% increase in contacts, but still not as much as Intel's transition (41.7%) from the LGA1200 socket to LGA1700 socket. The big question on everyone's mind is whether AM5 will warrant a CPU cooler upgrade.

One of, and perhaps the most important feature that consumers will be expecting from the AM5 socket is support for DDR5 memory. It's hard not to get excited when DDR5 is expected to feature capacities up to 128GB per memory module and data rates up to DDR5-10000. Intel's 12th Generation Alder Lake processors are projected to land late 2021 or early 2022 with support for DDR5. It's unlikely that the AM5 socket will come out before this year so it appears that Intel has beaten AMD to the DDR5 chase.

The leaker claims that the AM5 socket will retain support for PCIe 4.0. It makes perfect sense since the best graphics cards and best SSDs are far from saturating the PCIe 4.0 interface. Preparing for PCIe 5.0 will just add an unneeded premium to AM5 motherboards. A fresh, new socket typically commands a new chipset. In the case of the AM5 socket, we should expect AMD to launch the corresponding 600-series chipset along with the new platform and processors.

While we're on the topic of processors, AMD's Zen 4 chips (reportedly codenamed Raphael) will in all probability be the first products to leverage the AM5 socket. We still don't know a lot about Raphael, yet but we suspect that the processors should be product of TSMC's 5nm process node, similar to AMD's EPYC Genoa parts.

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Zhiye Liu
Zhiye Liu
News Editor and Memory Reviewer

Zhiye Liu is a news editor and memory reviewer at Tom’s Hardware. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.

21 Comments Comment from the forums
  • Kamen Rider Blade
    I think Pin Contacts may still be used, here's why:

    Socket AM4 Dimensions:

    Socket AM4 Pin LayOut: 1331 Pin Contacts
    Socket AM5 Pin Layout: 1520 Pin Contacts (Square Grid) <- HYPOTHETICAL


    Socket AM5 Pin Layout: 1732 Pin Contacts (Hexagonal Grid) <- HYPOTHETICAL

    There have been CPU's with nearly all Pin's on the underside
    https://en.wikipedia.org/wiki/Pin_grid_array
    The AMD Phenom X4 9750 on Socket AM2+ had nearly all Pins in a less dense PGA compared to today's PGA pin spacing.

    SPGA (Staggered Pin Grid Array) isn't a new concept.

    And on PGAs, bent pins are easier to repair and the MoBo isn't going to be useless if a pin gets bent on the MoBo in a LGA config.
    That's a huge advantage for AMD MoBo's compared to Intel's in terms of end user experience when installing the CPU.

    I think AMD will stick to it's PGA for Socket AM5, they can leave LGA for EPYC & ThreadRipper.

    The Heat Spreader can be the same size and they can just reuse the same mount as AM4.

    The Socket shape and pin-out would be the only thing that needs to change.

    That would leave it to the MoBo manufacturers to take care of things on their end, while the end user would have a superior experience of not needing new mounting hardware or new cooling since existing cooling solutions offer enough cooling for the existing TDP.

    And with new Process Nodes, they can just budget for the exact same TDP that AM4 has and call it a day since new process nodes brings more electrical & thermal efficiency, which should allow fore more cores and/or frequency.

    1732 Pins in a SPGA config is more than enough possible pins to use while removing a few pins to account for 1718 contacts.

    And in the future, if they need to add a few more Pins, like Intel, they can just increase the number of pins by a little bit.
    Reply
  • ottonis
    In order to keep the efficiency crown as well as an advantageous price to performance ratio, the transition to 5nm and production of sufficient amount of wafers by TSMC will be absolutely crucial.

    If AMD want to outsmart their competition, I hope they will also bake some partial hardware acceleration for contemporary video and audio codecs into their CPUs and thus keep video editing and multimedia tasks as efficient as Apple Silicon have demonstrated recently. Now that 4k Video 10bit 4:2:2 h265 has become the new "normal" in video production, and 8k just entering the room, hardware optimizations will be crucial to stay relevant in the multimedia field, where thousands and thousands of creators are jumping ship and changing to M1 based Apple computers that are playing back and scrubbing through 8k footage like a knife is cutting through warm butter.

    I also hope that that they will manage to "tune" their silicon for a larger latitude of efficiency vs performance, even without having to combine architecturally entirely distinct hybrid cores.
    For example they could have a chiplet with 4 cores tuned for ultra high efficiency (let's say at 5-10W) dealing with background OS tasks, networking, and I/O at 0.5-1GHz, while a high performance chiplet with 8-12 cores would do the heavy "muscle" work and be optimized for much higher frequency ranges and be allowed to suck in much more power (65-105W).
    Reply
  • everettfsargent
    " ... so take the information with a bit of salt. "

    I am and that so-called salt is bigger than this ...
    Archaeologists Discover The World's Largest Ancient Salt Grain To Be Repurposed For All TH Rumors.
    Reply
  • thGe17
    ottonis said:
    In order to keep the efficiency crown as well as an advantageous price to performance ratio, the transition to 5nm and production of sufficient amount of wafers by TSMC will be absolutely crucial.

    If AMD want to outsmart their competition, I hope they will also bake some partial hardware acceleration for contemporary video and audio codecs into their CPUs and thus keep video editing and multimedia tasks as efficient as Apple Silicon have demonstrated recently. Now that 4k Video 10bit 4:2:2 h265 has become the new "normal" in video production, and 8k just entering the room, hardware optimizations will be crucial to stay relevant in the multimedia field, where thousands and thousands of creators are jumping ship and changing to M1 based Apple computers that are playing back and scrubbing through 8k footage like a knife is cutting through warm butter.

    I also hope that that they will manage to "tune" their silicon for a larger latitude of efficiency vs performance, even without having to combine architecturally entirely distinct hybrid cores.
    For example they could have a chiplet with 4 cores tuned for ultra high efficiency (let's say at 5-10W) dealing with background OS tasks, networking, and I/O at 0.5-1GHz, while a high performance chiplet with 8-12 cores would do the heavy "muscle" work and be optimized for much higher frequency ranges and be allowed to suck in much more power (65-105W).
    Unless there is no iGPU, there will be no Media Acceleration Units, therefore you have to look at AMDs APUs for that. ;-)

    Additionally a "a chiplet with 4 cores" is an absolute waste of time and money. The chiplet-production is expensive for AMD and it would become even more expensive if they have to build different CCDs and even much smaller ones.
    On the contrary, I would expect the (one) 5nm-Zen4-CCD to increase in size to 12 cores per chip, therefore in 2022 AMD will only support the midrange and upper/high end with chiplet-based CPUs. For lower market segments you wil most likely have to buy an APU from AMD, because it is simply to expensive to provide chiplet-CPUs in this market segment at this price point.

    What a possible big.LITTLE implementation from AMD will look like in 2024+ ... who knows ...
    Reply
  • TheJoker2020
    It's not even up for debate, AM5 "IS" DDR5...

    As for whether AMD uses a Land Grid Array or not, if they do, I expect they would (for consumer products) use a "carrier" like is used on EPYC and Threadripper CPU's. Yes it adds to the cost, but it also reduces the cost for motherboard manufacturers (for consumer products) compared to PGA, where all of the RMA's and repairs went to AMD rather than the Mobo makers, and of course the greatest cost saving by far will be for the consumer who has a greatly reduced risk of destroying their motherboard (previously CPU), which play's into AMD's hands vs the competition. Just a thought "if" AMD does use an LGA CPU.
    Reply
  • InvalidError
    Kamen Rider Blade said:
    There have been CPU's with nearly all Pin's on the underside
    The closest you can put capacitors to the noise sources they are intended to bypass, the more effective they are, which is why the board area behind GPUs is packed with bypass caps. The less noise there is in the power supply, the less voltage headroom is needed for stable operation at a given frequency.

    I'd expect AMD to follow Intel's lead with AM5.
    Reply
  • ginthegit
    Kamen Rider Blade said:
    I think Pin Contacts may still be used, here's why:

    Socket AM4 Dimensions:

    Socket AM4 Pin LayOut: 1331 Pin Contacts
    Socket AM5 Pin Layout: 1520 Pin Contacts (Square Grid) <- HYPOTHETICAL


    Socket AM5 Pin Layout: 1732 Pin Contacts (Hexagonal Grid) <- HYPOTHETICAL

    There have been CPU's with nearly all Pin's on the underside
    https://en.wikipedia.org/wiki/Pin_grid_array
    The AMD Phenom X4 9750 on Socket AM2+ had nearly all Pins in a less dense PGA compared to today's PGA pin spacing.

    SPGA (Staggered Pin Grid Array) isn't a new concept.

    And on PGAs, bent pins are easier to repair and the MoBo isn't going to be useless if a pin gets bent on the MoBo in a LGA config.
    That's a huge advantage for AMD MoBo's compared to Intel's in terms of end user experience when installing the CPU.

    I think AMD will stick to it's PGA for Socket AM5, they can leave LGA for EPYC & ThreadRipper.

    The Heat Spreader can be the same size and they can just reuse the same mount as AM4.

    The Socket shape and pin-out would be the only thing that needs to change.

    That would leave it to the MoBo manufacturers to take care of things on their end, while the end user would have a superior experience of not needing new mounting hardware or new cooling since existing cooling solutions offer enough cooling for the existing TDP.

    And with new Process Nodes, they can just budget for the exact same TDP that AM4 has and call it a day since new process nodes brings more electrical & thermal efficiency, which should allow fore more cores and/or frequency.

    1732 Pins in a SPGA config is more than enough possible pins to use while removing a few pins to account for 1718 contacts.

    And in the future, if they need to add a few more Pins, like Intel, they can just increase the number of pins by a little bit.

    Agreed, I dont really understand the facination with the BGA. You have to have pins somewhere, and better on the chip than the motherboard.
    Pins are a difficult things to repair when you bend some, but if you are careful, then this is no issue.
    Reply
  • ginthegit
    ottonis said:
    In order to keep the efficiency crown as well as an advantageous price to performance ratio, the transition to 5nm and production of sufficient amount of wafers by TSMC will be absolutely crucial.

    If AMD want to outsmart their competition, I hope they will also bake some partial hardware acceleration for contemporary video and audio codecs into their CPUs and thus keep video editing and multimedia tasks as efficient as Apple Silicon have demonstrated recently. Now that 4k Video 10bit 4:2:2 h265 has become the new "normal" in video production, and 8k just entering the room, hardware optimizations will be crucial to stay relevant in the multimedia field, where thousands and thousands of creators are jumping ship and changing to M1 based Apple computers that are playing back and scrubbing through 8k footage like a knife is cutting through warm butter.

    I also hope that that they will manage to "tune" their silicon for a larger latitude of efficiency vs performance, even without having to combine architecturally entirely distinct hybrid cores.
    For example they could have a chiplet with 4 cores tuned for ultra high efficiency (let's say at 5-10W) dealing with background OS tasks, networking, and I/O at 0.5-1GHz, while a high performance chiplet with 8-12 cores would do the heavy "muscle" work and be optimized for much higher frequency ranges and be allowed to suck in much more power (65-105W).

    In part I think they do. CISC is by definition hardwiring Combinational logic and sequential logic systems to support new instruction sets.
    Reply
  • ginthegit
    InvalidError said:
    The closest you can put capacitors to the noise sources they are intended to bypass, the more effective they are, which is why the board area behind GPUs is packed with bypass caps. The less noise there is in the power supply, the less voltage headroom is needed for stable operation at a given frequency.

    I'd expect AMD to follow Intel's lead with AM5.

    apart form command standards, and hardware standards, AMD have kept themselves away from Intels often nonsense tech. AMD should just keep things simple and progress with their own way to interconnect between new hardware. They always have and always will. They haven't been bullied by intel in the past, and wont start now!
    Reply
  • ginthegit
    InvalidError said:
    The closest you can put capacitors to the noise sources they are intended to bypass, the more effective they are, which is why the board area behind GPUs is packed with bypass caps. The less noise there is in the power supply, the less voltage headroom is needed for stable operation at a given frequency.

    I'd expect AMD to follow Intel's lead with AM5.
    Heh! I think he is talking about the Pins on the bottom on the Chips as opposed to Intels BGA approach. Tells me you havent really owned an AMD chip. Not recently anyway.

    Not sure ho what he says relates to the use of Filtering capacitors between the power plane and the ground plane. Although these would be more in use if they adopted the 12VO approach.
    Reply