Intel's 12th-Gen Alder Lake chip will bring the company's hybrid architecture, which combines a mix of larger high-performance cores paired with smaller high-efficiency cores, to desktop x86 PCs for the first time. That represents a massive strategic shift as Intel looks to regain the uncontested performance lead against AMD's Ryzen 5000 series processors. AMD's Zen 3 architecture has taken the lead in our Best CPUs and CPU Benchmarks hierarchy, partly on the strength of their higher core counts. That's not to mention Apple's M1 processors that feature a similar hybrid design and come with explosive performance improvements of their own.
Intel's Alder Lake brings disruptive new architectures and reportedly supports features like PCIe 5.0 and DDR5 that leapfrog AMD and Apple in connectivity technology and also outstrip Ryzen's core counts in mobile designs, but the new chips come with significant risks. It all starts with a new way of thinking, at least as far as x86 chips are concerned, of pairing high-performance and high-efficiency cores within a single chip. That well-traveled design philosophy powers billions of Arm chips, often referred to as Big.Little (Intel calls its implementation Big-Bigger), but it's a first for x86 desktop PCs.
Intel has confirmed that its Golden Cove architecture powers Alder Lake's 'big' high-performance cores, while the 'small' Atom efficiency cores come with the Gracemont architecture, making for a dizzying number of possible processor configurations. Intel will etch the cores on its 10nm Enhanced SuperFin process, marking the company's first truly new node for the desktop since 14nm debuted six long years ago.
As with the launch of any new processor, Intel has a lot riding on Alder Lake. However, the move to a hybrid architecture is unquestionably riskier than prior technology transitions because it requires operating system and software optimizations to achieve maximum performance and efficiency. It's unclear how unoptimized code will impact performance.
In either case, Intel is going all-in: Intel will reunify its desktop and mobile lines with Alder Lake, and we could even see the design come to the company's high-end desktop (HEDT) lineup. Intel has even listed -N variants for the educational (Chromebooks) segment, indicating that Alder Lake will span its entire stack of chips.
Intel might have a few tricks up its sleeve, though. Intel paved the way for hybrid x86 designs with its Lakefield chips, the first such chips to come to market, and established a beachhead in terms of both Windows and software support. Lakefield really wasn't a performance stunner, though, due to a focus on lower-end mobile devices where power efficiency is key. In contrast, Intel says it will tune Alder Lake for high-performance, a must for desktop PCs and high-end notebooks. There are also signs that some models will come with only the big cores active, which should perform exceedingly well in gaming.
Meanwhile, Apple's potent M1 processors with their Arm-based design have brought a step function improvement in both performance and power consumption over competing x86 chips. Much of that success comes from Arm's long-standing support for hybrid architectures and the requisite software optimizations. Comparatively, Intel's efforts to enable the same tightly-knit level of support are still in the opening stages.
Potent adversaries challenge Intel on both sides. Apple's M1 processors have set a high bar for hybrid designs, outperforming all other processors in their class with the promise of more powerful designs to come. Meanwhile, AMD's Ryzen 5000 chips have taken the lead in every metric that matters over Intel's aging Skylake derivatives.
Intel certainly needs a come-from-behind design to thoroughly unseat its competitors, swinging the tables back in its favor like the Conroe chips did back in 2006 when the Core architecture debuted with a ~40% performance advantage that cemented Intel's dominance for a decade. Intel's Raja Koduri has already likened the transition to Alder Lake with the debut of Core, suggesting that Alder Lake could indeed be a Conroe-esque moment.
In the meantime, Intel's Rocket Lake has arrived, and while the new chips overtake AMD in single-threaded performance, they still trail in multi-core workloads due to Rocket Lake's maximum of eight cores, while AMD has 16-core models for the mainstream desktop. That makes Alder Lake exceedingly important as Intel looks to regain its performance lead in the desktop PC and laptop markets.
While Intel hasn't shared many of the details on the new chip, plenty of unofficial details have come to light over the last few months, giving us a broad indication of Intel's vision for the future. Let's dive in.
Intel's 12th-Gen Alder Lake At a Glance
- Qualification and production in the second half of 2021
- Hybrid x86 design with a mix of big and small cores (Golden Cove/Gracemont)
- Up to 16 cores
- 10nm Enhanced SuperFin process
- LGA1700 socket requires new motherboards
- PCIe 5.0 and DDR5 support rumored
- Four variants: -S for desktop PCs, -P for mobile, -M for low-power devices, -L Atom replacement, -N educational (probably Chromebooks)
- Gen12 Xe integrated graphics
- New hardware-guided operating system scheduler tuned for high performance
Intel Alder Lake Release Date
Intel hasn't given a specific date for Alder Lake's debut, but it has said that the chips will be validated for production for desktop PCs and notebooks with the volume production ramp beginning in the second half of the year. That means the first salvo of chips could land in late 2021, though it might also end up being early 2022. Given the slew of benchmark submissions and operating system patches we've seen, like this new benchmark of a 14-core model for laptops, early silicon is obviously already in the hands of OEMs and various ecosystem partners.
Intel and its partners also have plenty of incentive to get the new platform and CPUs out as soon as possible, and we could have a similar situation to 2015's short-lived Broadwell desktop CPUs that were almost immediately replaced by Skylake. Rocket Lake seems competitive on performance, but the existing Comet Lake chips (e.g. i9-10900K) already use a lot of power, and i9-11900K doesn't look to change that. With 10nm Enhanced SuperFIN, Intel could dramatically cut power requirements while improving performance.
Intel Alder Lake Specifications and Families
Intel hasn't released the official specifications of the Alder Lake processors, but a recent update to the SiSoft Sandra benchmark software, along with listings to the open-source Coreboot (a lightweight motherboard firmware option), have given us plenty of clues to work with.
The Coreboot listing outlines various combinations of the big and little cores in different chip models, with some models even using only the larger cores (possibly for high-performance gaming models). The information suggests four configurations with -S, -P, -N, and -M designators, and an -L variant has also emerged:
- Alder Lake-S: Desktop PCs (Both LGA and BGA models)
- Alder Lake-P: High-performance notebooks
- Alder Lake-M: Low-power devices
- Alder Lake-L: Listed as "Small Core" Processors (Atom)
- Alder Lake-N: Educational and consumer client (Chromebook-class devices)
Intel Alder Lake-S Desktop PC Specifications
|Big + Small Cores||Cores / Threads||GPU|
|8 + 8||16 / 24||GT1 - Gen12 32EU|
|8 + 6||14 / 22||GT1 - Gen12 32EU|
|8 + 4||12 / 20||GT1 - Gen12 32EU|
|8 + 2||10 / 18||GT1 - Gen12 32EU|
|8 + 0||8 / 16||GT1 - Gen12 32EU|
|6 + 8||14 / 20||GT1 - Gen12 32EU|
|6 + 6||12 / 18||GT1 - Gen12 32EU|
|6 + 4||10 / 16||GT1 - Gen12 32EU|
|6 + 2||8 / 14||GT1 - Gen12 32EU|
|6 + 0||6 / 12||GT1 - Gen12 32EU|
|4 + 0||4 / 8||GT1 - Gen12 32EU|
|2 + 0||2 / 4||GT1 - Gen12 32EU|
*Intel has not officially confirmed these configurations. Not all models may come to market. Listings assume all models have Hyper-Threading enabled on the large cores.
Intel's 10nm Alder Lake combines large Golden Cove cores that support Hyper-Threading (Intel's branded version of SMT, symmetric multi-threading, that allows two threads to run on a single core) with smaller single-threaded Atom cores. That means some models could come with seemingly-odd distributions of cores and threads. We'll jump into the process technology a bit later.
As we can see above, a potential flagship model would come with eight Hyper-Threading enabled 'big' cores and eight single-threaded 'small' cores, for a total of 24 threads. Logically we could expect the 8 + 8 configuration to fall into the Core i9 classification, while 8 + 4 could land as Core i7, and 6 + 8 and 4 + 0 could fall into Core i5 and i3 families, respectively. Naturally, it's impossible to know how Intel will carve up its product stack due to the completely new paradigm of the hybrid x86 design.
We're still quite far from knowing particular model names, as recent submissions to public-facing benchmark databases list the chips as "Intel Corporation Alder Lake Client Platform" but use '0000' identifier strings in place of the model name and number. This indicates the silicon is still in the early phases of testing, and newer steppings will eventually progress to production-class processors with identifiable model names.
Given that these engineering samples (ES) chips are still in the qualification stage, we can expect drastic alterations to clock rates and overall performance as Intel dials in the silicon. It's best to use the test submissions for general information only, as they rarely represent final performance.
The 16-core desktop model has been spotted in benchmarks with a 1.8 GHz base and 4.0 GHz boost clock speed, but we can expect that to increase in the future. For example, a 14-core 20-thread Alder Lake-P model was recently spotted at 4.7 GHz. We would expect clock rates to be even higher for the desktop models, possibly even reaching or exceeding 5.0 GHz on the 'big' cores due to a higher thermal budget.
Meanwhile, it's widely thought that the smaller efficiency cores will come with lower clock rates, but current benchmarks and utilities don't enumerate the second set of cores with a separate frequency domain, meaning we'll have to wait for proper software support before we can learn clock rates for the efficiency cores.
For graphics duties, Intel will include GT1 Xe configurations that top out at 32 EUs. That's 33% more than the current desktop chips with Gen9.5 UHD 630 Graphics, but a far cry from the 96 EUs found in 11th Gen Tiger Lake. But this is on the desktop, where most users that care about graphics performance will simply use a dedicated GPU.
We do know from Coreboot patches that Alder Lake-S supports two eight-lane PCIe 5.0 connections and two four-lane PCIe 4.0 connections, for a total of 24 lanes. Conversely, Alder Lake-P dials back connectivity due to its more mobile-centric nature and has a single eight-lane PCIe 5.0 connection along with two four-lane PCIe 4.0 interfaces. There have also been concrete signs of support for DDR5 memory. There are some caveats, though, which you can read about in the motherboard section.
Intel Alder Lake-P and Alder Lake-M Mobile Processor Specifications
|Big + Small Cores||Cores / Threads||GPU|
|6 + 8||14 / 20||GT2 Gen12 96EU|
|6 + 4||10 / 14||GT2 Gen12 96EU|
|4 + 8||12 / 16||GT2 Gen12 96EU|
|2 + 8||10 / 12||GT2 Gen12 96EU|
|2 + 4||6 / 8||GT2 Gen12 96EU|
|2 + 0||2 / 4||GT2 Gen12 96EU|
*Intel has not officially confirmed these configurations. Not all models may come to market. Listings assume all models have Hyper-Threading enabled on the large cores.
The Alder Lake-P processors are listed as laptop chips, so we'll probably see those debut in a wide range of notebooks that run the gamut from thin-and-light form factors up to high-end gaming notebooks.
As you'll notice above, all of these processors purportedly come armed with Intel's Gen 12 Xe architecture in a GT2 configuration, imparting 96 EUs across the range of chips. That's triple the execution units over the desktop chips and could indicate a focus on reducing the need for discrete graphics chips. What we've seen from current 96 EU Xe solutions (i.e. Tiger Lake) suggests performance that might be on the level of a GT 1030, however, so count on gaming laptops including dedicated GPUs.
There is precious little information available for the -M variants, but they're thought to be destined for lower-power devices and serve as a replacement for Lakefield chips. We do know from recent patches that Alder Lake-M comes with reduced I/O support, which we'll cover below.
Finally, an Alder Lake-L version has been added to the Linux kernel, classifying the chips as '"Small Core" Processors (Atom),' but we haven't seen other mentions of this configuration elsewhere. Alder Lake-N has also been listed by Intel, and it will target the educational segment.
Intel Alder Lake 600-Series Motherboards, LGA1700 Socket, DDR5 and PCIe 5.0
Intel's incessant motherboard upgrades, which require new sockets or restrict support within existing sockets, have earned the company plenty of criticism from the enthusiast community — especially given AMD's long line of AM4-compatible processors. That trend will continue with a new requirement for LGA1700 sockets and the 600-series chipset for Alder Lake. Still, if rumors hold true, Intel will stick to the new socket for at least the next generation of processors (7nm Meteor Lake) and possibly for an additional generation beyond that, rivaling AMD's AM4 longevity.
Last year, an Intel document revealed an LGA1700 interposer for its Alder Lake-S test platform, confirming that the rumored socket will likely house the new chips. Months later, an image surfaced at VideoCardz, showing an Alder Lake-S chip and the 37.5 x 45.0mm socket dimensions. That's noticeably larger than the current-gen LGA1200's 37.5 x 37.5mm.
Because the LGA1700 socket is bigger than the current sockets used in LGA1151/LGA1200 motherboards, existing coolers may be incompatible, but we expect that cooler conversion kits could accommodate the larger socket. (Coolers that support both LGA11xx and LGA2066 already exist, so an in-between option shouldn't be too difficult.) The larger socket is needed to accommodate 500 more pins than the LGA1200 socket. Those pins are needed to support newer interfaces, like PCIe 5.0 and DDR5, among other purposes, like power delivery. Intel has also listed Alder Lake-S BGA support documentation, indicating that soldered-down models will also come to market.
PCIe 5.0 and DDR5 support are both listed in patch notes, possibly giving Intel a connectivity advantage over competing chips, but there are a lot of considerations involved with these big technology transitions. As we saw with the move from PCIe 3.0 to 4.0, a step up to a faster PCIe interface requires thicker motherboards (more layers) to accommodate wider lane spacing, more robust materials, and retimers due to stricter trace length requirements. All of these factors conspire to increase cost.
We recently spoke with Microchip, which develops PCIe 5.0 switches, and the company tells us that, as a general statement, we can expect those same PCIe 4.0 requirements to become more arduous for motherboards with a PCIe 5.0 interface, particularly because they will require retimers for even shorter lane lengths and even thicker motherboards. That means we could see yet another jump in motherboard pricing over what the industry already absorbed with the move to PCIe 4.0. Additionally, PCIe 5.0 also consumes more power, which will present challenges in mobile form factors.
Both Microchip and the PCI-SIG standards body tell us that PCIe 5.0 adoption is expected to come to the high-performance server market and workstations first, largely because of the increased cost and power consumption. That isn't a good fit for consumer devices considering the slim performance advantages in lighter workloads. That means that while Alder Lake may support PCIe 5.0, it's possible that we could see the first implementations run at standard PCIe 4.0 signaling rates.
Intel took a similar tactic with its Tiger Lake processors — while the chip's internal pathways are designed to accommodate the increased throughput of the DDR5 interface via a dual ring bus, they came to market with DDR4 memory controllers, with the option of swapping in new DDR5 controllers in the future. We could see a similar approach with PCIe 4.0, with the first devices using existing controller tech, or the PCIe 5.0 controllers merely defaulting to PCIe 4.0.
Benchmarks have surfaced that indicate that Alder Lake supports DDR5 memory, but like the PCIe 5.0 interface, but it also remains to be seen if Intel will enable it on the leading wave of processors. Notably, every transition to a newer memory interface has resulted in higher up-front DIMM pricing, which is concerning in the price-sensitive desktop PC market. DDR4 for example first came to the HEDT segment on Intel's X99 platform in 2014, and pricing at the time was more than double the cost of DDR3. Skylake brought DDR4 to the mainstream segment in 2015, but it still carried a 25-50% price premium.
DDR5 is in the opening stages; some vendors, like Adata, TeamGroup, and Micron, have already begun shipping modules. The inaugural modules are expected to run in the DDR5-4800 to DDR5-6400 range. The JEDEC spec tops out at DDR5-8400, but as with DDR4, it will take some time before we see those peak speeds. Notably, several of these vendors have reported that they don't expect the transition to DDR5 to happen until early 2022.
We have, however, seen signs that only the higher-end Alder Lake desktop PC platforms, like Z-series motherboard, will support DDR5, while lower-end B- and H-series boards will use DDR4 for a friendlier price of entry. There have also been concrete reports that Intel will continue to use its new Gear 1 and Gear 2 memory alignment with Alder Lake. You can read more about this memory alignment, and the pros and cons, here.
While the details are hazy around the separation of the Alder Lake-S, -P, -M, and -L variants, some details have emerged about the I/O allocations via Coreboot patches:
|Alder Lake-P||Alder Lake-M||Alder Lake-S|
|CPU PCIe||One PCIe 5.0 x8 / Two PCIe 4.0 x4||Unknown||Two PCIe 5.0 x8 / Two PCIe 4.0 x4|
|PCH PCIe Ports||12||10||28|
We don't have any information for the Alder Lake-L configuration, so it remains shrouded in mystery. However, as we can see above, the PCIe, PCH, and SATA allocations vary by the model, based on the target market. Notably, the Alder Lake-P configuration is destined for mobile devices.
One interesting piece of information we don't know yet is how Alder Lake CPUs will connect to the PCH. Current Intel processors use a DMI 3.0 link that's basically equivalent (in bandwidth) to x4 PCIe Gen3 — 4GBps bidirectional bandwidth. The upcoming Z590 boards double the link width to x8 (8GBps), keeping speeds at PCIe Gen3. Alder Lake will likely keep the x8 link width, considering all the extra pins, but could potentially use Gen4 or Gen5 data rates. Gen4 seems more likely, as even that would represent four times the CPU to PCH bandwidth compared to the current mainstream platforms.
Also notably lacking on the information currently in the wild is any indication of TDP (Thermal Design Power). It's no secret Intel has been struggling badly with TDP on its most recent desktop processors. The i9-9900K was the last 'sensible' chip at the top of Intel's product stack, with the i9-10900K capable of using 250W. We expect the same 250W max power use from Rocket Lake's i9-11900K. But Alder Lake should greatly improve the situation — though it's difficult to imagine how it could possibly be worse.
Traditionally, Intel has targeted a top TDP of around 95W for its mainstream CPUs, and we'd like to see a return of that approach. With the Enhanced SuperFIN 10nm process, Golden Cove high-performance cores, and Gracemont efficiency-focused cores, plus a larger IHS (integrated heatspreader) due to the larger socket, we expect Alder Lake to be far more competitive in TDP.
Additionally, the new desktop PC motherboards for Alder Lake chips will herald the arrival of mainstream ATX12VO motherboards that leverage a new lower-power PSU specification. Both systems with support for standard power supplies and the ATX12VO spec are planned, but Intel is on a full-court press to push adoption of the new standard.
Intel 12th-Gen Alder Lake Xe LP Integrated Graphics
A series of Geekbench test submissions have given us a rough outline of the graphics accommodations for a few of the Alder Lake chips. Recent Linux patches indicate the chips feature the same Gen12 Xe LP architecture as Tiger Lake, though there is a distinct possibility of a change to the sub-architecture (12.1, 12.2, etc.). Also, there are listings for a GT0.5 configuration in Intel's media driver, but that is a new paradigm in Intel's naming convention so we aren't sure of the details yet.
The Alder Lake-S processors come armed with the 32 EUs (256 shaders) in a GT1 configuration, and the iGPU on early samples runs at 1.5 GHz. We've also seen Alder Lake-P benchmarks with the GT2 configuration, with 96 EUs (768 shaders). The early Xe LP iGPU silicon on the -P model runs at 1.15GHz, but as with all engineering samples, that could change with shipping models.
Alder Lake's integrated GPUs support up to five display outputs (eDP, dual HDMI, and Dual DP++), and support the same encoding/decoding features as both Rocket Lake and Tiger Lake, including AV1 8-bit and 10-bit decode, 12-bit VP9, and 12-bit HEVC.
Intel Alder Lake CPU Architecture and 10nm Enhanced SuperFin Process
Intel pioneered the x86 hybrid architecture with its Lakefield chips, with those inaugural models coming with one Sunny Cove core paired with four Atom Tremont cores.
Compared to Lakefield, both the high- and low-performance Alder Lake-S cores take a step forward to newer microarchitectures. Alder Lake-S actually jumps forward two 'Cove' generations compared to the 'big' Sunny Cove cores found in Lakefield. The big Golden Cove cores come with increased single-threaded performance, AI performance, Network and 5G performance, and improved security features compared to the Willow Cove cores that debuted with Tiger Lake.
Alder Lake's smaller Gracemont cores jump forward a single Atom generation and offer the benefit of being more power and area efficient (perf/mm^2) than the larger Golden Cove cores. Gracemont also comes with increased vector performance, a nod to an obvious addition of some level of AVX support (likely AVX2). Intel also lists improved single-threaded performance for the Gracemont cores.
It's unclear whether Intel will use its Foveros 3D packaging for the chips. This 3D chip-stacking technique reduces the footprint of the chip package, as seen with the Lakefield chips. However, given the large LGA1700 socket, that type of packaging seems unlikely for the desktop PC variants. We could see some Alder Lake-P, -M, or -L chips employ Foveros packaging, but that remains to be seen.
Lakefield served as a proving ground not only for Intel's 3D Foveros packaging tech but also for the software and operating system ecosystem. At its Architecture Day, Intel outlined the performance gains above for the Lakefield chips to highlight the promise of hybrid designs. Still, the results come with an important caveat: These types of performance improvements are only available through both hardware and operating system optimizations.
Due to the use of both faster and slower cores that are optimized for different voltage/frequency profiles, unlocking the maximum performance and efficiency requires the operating system and applications to have an awareness of the chip topology to ensure workloads (threads) land in the correct core based on the type of application.
For instance, if a latency-sensitive workload like web browsing lands in a slower core, performance will suffer. Likewise, if a background task is scheduled into a fast core, some of the potential power efficiency gains are lost. There's already work underway in both Windows and various applications to support that technique via a hardware-guided OS scheduler.
The current format for Intel's Lakefield relies on both cores supporting the same instruction set. Alder Lake's larger Golden Cove cores support AVX-512, but it appears that those instructions will be disabled to accommodate the fact that the Atom Gracemont cores do not support the instructions. There is a notable caveat that any of the SKUs that come with only big cores might still support the instructions.
Intel Chief Architect Raja Koduri mentioned that a new "next-generation" hardware-guided OS scheduler that's optimized for performance would debut with Alder Lake, but didn't provide further details. This next-gen OS scheduler could add in support for targeting cores with specific instruction sets to support a split implementation, but that remains to be seen, and early signs in Linux patches point to support for a single ISA subset across both types of cores.
Intel fabs Alder Lake on its Enhanced 10nm SuperFin process. This is the second-generation of Intel's SuperFin process, which you can learn more about in our deep-dive coverage.
Intel says the first 10nm SuperFin process provides the largest intra-node performance improvement in the company's history, unlocking higher frequencies and lower power consumption than the first version of its 10nm node. Intel says the net effect is the same amount of performance uplift that the company would normally expect from a whole series of intra-node "+" revisions, but in just one shot. As such, Intel claims these transistors mark the largest single intra-node improvement in the company's history.
The 10nm SuperFin transistors have what Intel calls breakthrough technology that includes a new thin barrier that reduces interconnect resistance by 30%, improved gate pitch so the transistor can drive higher current, and enhanced source/drain elements that lower resistance and improve strain. Intel also added a Super MIM capacitor that drives a 5X increase in capacitance, reducing vDroop. That's important, particularly to avoid localized brownouts during heavy vectorized workloads and also to maintain higher clock speeds.
During its Architecture Day, Intel teased the next-gen variant of SuperFin, dubbed '10nm Enhanced SuperFin,' saying that this new process was tweaked to increase interconnect and general performance, particularly for data center parts (technically, this is 10nm+++, but we won't quibble over an arguably clearer naming convention). This is the process used for Alder Lake, but unfortunately, Intel's descriptions were vague, so we'll have to wait to learn more.
We know that the 16-core models come armed with 30MB of L3 cache, while the 14-core / 24 thread chip has 24MB of L3 cache and 2.5 MB of L2 cache. However, it is unclear how this cache is partitioned between the two types of cores, which leaves many questions unanswered.
Alder Lake also supports new instructions, like Architectural LBRs, HLAT, and SERIALIZE commands, which you can read more about here. Alder Lake also purportedly supports AVX2 VNNI, which "replicates existing AVX512 computational SP (FP32) instructions using FP16 instead of FP32 for ~2X performance gain." This rapid math support could be part of Intel's solution for the lack of AVX-512 support for chips with both big and small cores, and although it hasn't been officially confirmed, early signs point to just this type of implementation.
Intel 12th-Generation Alder Lake Price
Intel's Alder Lake is likely at least 8-10 months away, so pricing is the wild card. Intel has boosted its 10nm production capacity tremendously over the course of 2020 and hasn't suffered any recent shortages of its 10nm processors. That means that Intel should have enough production capacity to keep costs within reasonable expectations, but predicting Intel's future 10nm supply simply isn't reasonable given the complete lack of substantive information on the matter.
However, Intel has proven with its Comet Lake, Ice Lake, and Cooper Lake processors that it is willing to lose margin in order to preserve its market share, and surprisingly, Intel's recent price adjustments have given Comet Lake a solid value proposition compared to AMD's Ryzen 5000 chips.
We can only hope that trend continues, but if Alder Lake brings forth both PCIe 5.0 and DDR5 support as expected, we could be looking at exceptionally pricey memory and motherboard accommodations.