HyperTransport: A High-speed Bus Without Detours
Unlike all Intel CPUs, which communicate with the Northbridge via a regular parallel FSB, AMD's Hammer relies on a HyperTransport interface. The serial interface with a variable bitrate allows the SledgeHammer to attain a data transfer rate of 3.2 GB/s - in both directions simultaneously. This results in a total bandwidth of 6.4 GB/s. By comparison, the Pentium 4 with 533 MHz FSB allows a maximum data throughput of 3.97 GB/s - but not in both directions simultaneously. The bandwidth of the serial interface is designed to be flexible. AMD gives the server version of the Hammer three HyperTransport ports. The entire data traffic of the Hammer processor runs through the HyperTransport interface and the integrated memory controller. In order to let the neighboring CPU gain direct access to its system memory, the Hammer uses the XBAR switch. For commands and addresses, the XBAR switch has further 64 bit buses available.
Athlon 64/FX: Five Different Modes Of Operation
The five different modes of the AMD 64/FX.
Depending which bits are set in the LME register, the processor works in one of the operating modes depicted here. This ensures backwards compatibility.
Register: 32 Bit & 64 Bit
Although it sounds like significantly less than the 64 bits one might expect from the name, the x86-64 comes with a 40 bit wide physical address space and a 48 bit wide virtual address space. This limits the system memory to 1 TB (1024 GB). New in Hammer: the x86-64 architecture extends the 32 bit register of the IA-32 processors to 64 bit. With applications that run in legacy or compatibility modes, the Hammer can continue to use only the eight conventional 32 bit wide registers EAX, EBX, ECX, EDX, EBP, ESI, EDI and ESP (see graphic above). If the processor works in 64 bit mode, then the x86-64 architecture extends these eight registers via the "R" prefix to 64 bit. The extended registers are then named RAX to RSP. In addition, in 64 bit mode, the Hammer can access another eight GPRs (General Purpose Registers) R8 to R15, which are also 64 bit wide each. For floating point calculations, the eight 128 bit wide SSE registers have been doubled with XMM8 to XMM15. Once again, only the 64 bit mode profits from this.
|Athlon XP||Athlon 64 (FX)|
|Operating Mode||32 bit Mode||32 bit Mode (Legacy or Compatibility Mode)||64 bit Mode|
|GPRs||8x (32 bit)||8x (32 bit)||16x (64 bit)|
|SSE registers||8x (128 bit)||8x (128 bit)||16x (128 bit)|
|MMX registers||8x (64 bit)||8x (64 bit)||8x (64 bit)|
|x87 registers||8x (80 bit)||8x (80 bit)||8x (80 bit)|
The Athlon 64 (FX) presents the operating system with the same number of registers as the old Athlon XP when operating only in 32 bit mode. More registers are only available in 64 bit mode. Enhanced performance is therefore only possible if the memory interface is reworked.