Socket 462 Gets Replaced: Sockets 745 And 940/939
Socket 462 has been around for a long time. However, with the launch of the Athlon 64 series, Socket 462's days are numbered. The "normal" Athlon 64 is based on the new Socket 754, and the Athlon 64 FX has to be plugged into Socket 940. The different pin count of the two Hammer CPUs is due to the fact that the Athlon 64 FX has a dual-channel memory interface as well as three HyperTransport ports. The standard Athlon 64 only has one single-channel memory interface and one HyperTransport port. The mPGA packaging, similar to that of the Intel Pentium 4 and Xeon, is common to all Hammer processors.
Integrated Memory Interface: No Northbridge Meddling
The concept of the Hammer multi-processor systems includes local memory on each CPU so that the other CPUs can access the memory of these CPUs via the HyperTransport bus. Initially, only the server version of the Hammer, the Opteron, will be equipped with two 72 bit wide DDR SDRAM channels. With a total of eight DIMM slots, this allows each processor to address 8 GB. The dual-channel interface of the Athlon 64 FX-51 offers a memory bandwidth of 6.4 GB/s. Still, the integration of the memory controller can also be considered as a limitation on flexibility.
Controlling Costs: Production Of Athlon 64/FX In Dresden
On site in Dresden: Only a stone's throw away at the same production site, Infineon is already working on wafers with diameters of 300mm. At AMD it's taking a little longer. Currently only wafers with diameters of 200mm are serving as the basis for the manufacture of Athlon XP and Hammer CPUs. Both the Barton (Athlon XP) and Hammer types (Athlon 64, FX, Opteron, Mobile Athlon 64) are based on structures 130 nanometers wide. In order to hold their own against future competition, cost reductions must be made in production. This issue can be resolved for one by using larger wafers (300mm) and further by using thinner structures. With the launch of the P4 successor Prescott, rival Intel plans to be the world's first manufacturer to rely on 90 nanometers. AMD is not at that point yet and is considering launching its 90-nanometer technology in mid-2004. Purely from a cost point of view, the 90-nanometer technology will cause an increase in yield per wafer and, ultimately, lower die costs.
|CPU core||Wafer costs||Die material||Package costs||Packaging & Tests||Total cost of die|
Manufacturing specialists in Dresden simply calculate the die costs from the wafer costs and the number of CPU dies per wafer. Add to that the costs for packaging, testing and assembly. Just a side note: Among process specialists, a price of about $3000 per wafer has been mentioned. This allows the costs for 130-nanometer dies to be calculated quite precisely. Our table shows the cost difference (pure material costs without actual packaging with pins) between Barton and Hammer dies.
The main goal of AMD should be to gain control of both margin and unit price for the Hammer and simultaneously to lower production costs. After all, lower total costs in production mean more flexibility in pricing for the chip manufacturer, particularly when high unit counts are necessary for the low-end segment. The mass market expects competitive processors, while the Opteron, which is strong on image, should ensure greater acceptance among the OEMs.