DDR2 SLI Memory: 10.3 GB Per Second
The AM2 CPUs are designed to take a maximum memory clock of DDR2 800. This is not the most attractive prospect for overclockers, of course, since there are already memory modules out there running at up to DDR2 1066. The name promises great things, but the idea is actually quite simple.
Stores will be carrying these special memory modules, which are simply called "SLI memory." Nvidia has partnered with memory manufacturer Corsair to bring these to market. The technology is an open standard, so other manufacturers can also offer these SLI modules. Corsair has announced that in the future all XMS2 modules will have the SLI function.
Corsair’s SLI memory is still a pre-test sample and has the name printed on it.
How Does SLI Memory Work ?
In the memory module, several overclocking profiles are stored, which can be selected via the BIOS.
SLI memory settings in BIOS : With some BIOS versions, this is only visible when SLI memory is being used.
In the memory modules’ serial presence detect (SPD) EEPROM, which stores information about the module along with its speed and timings, additional data is entered, resulting in these profiles.
SPD data is stored in this little EEPROM - with SLI memory, additional data is also included.
The corresponding standard is called Enhanced Performance Profiles (EPP). There’s only room for two of these profiles in the EEPROM, since it has very little storage space. Two complete sets of data can be stored, but it is also possible to burn up to four reduced versions (with less data) onto the EEPROM. The following table shows you the information that can be stored.
| EPP Memory Information in EEPROM | ||
|---|---|---|
| Available Data | Complete Version | Reduced Version |
| Voltage Level | X | X |
| Address Cmd Rate | X | X |
| Chip Select Drive Strength | X | Row 3 - Cell 2 |
| Clock Drive Strength | X | Row 4 - Cell 2 |
| Data Drive Strength | X | Row 5 - Cell 2 |
| DQS Drive Strength | X | Row 6 - Cell 2 |
| Address/Command Fine Delay | X | Row 7 - Cell 2 |
| Address/Command Setup Time | X | Row 8 - Cell 2 |
| Chip Select Delay | X | Row 9 - Cell 2 |
| Chip Select Setup Time | X | Row 10 - Cell 2 |
| Minimum Cycle at Sup. CAS Latency | X | X |
| CAS Latency | X | X |
| Minimum RAS to CAS delay (tRCD) | X | X |
| Minimum Row Precharge Time (tRP) | X | X |
| Minimum Active to Precharge Time (tRAS) | X | X |
| Write Recovery Time (tWR) | X | Row 16 - Cell 2 |
| Minimum Active to Active/Refresh Time (tRC) | X | Row 17 - Cell 2 |
