Top Secret Intel Processor Plans Uncovered

Merom Is The Mother Of All Upcoming Processor Designs

So far Intel has announced three processor versions that are expected to be launched in fall of 2006. Conroe will be the desktop processor for Socket 775, featuring two cores and a shared 4 MB L2 cache. There will be a server processor that is based on the same chip architecture and cache size whose name is Woodcrest.

Both share the same genes that are derived from the processor design that is looked forward to as Merom. This one will power new mobile processors with either 2 MB or 4 MB L2 cache and two cores sharing it. A Woodcrest version with 8 MB cache that was being shown on some slides during the last Intel Developer Forum isn't mentioned any longer.

All chips based on the Merom design will use 65 nm technology and are expected to outperform the competition both in raw speed and raw speed per Watt. The manufacturing process is called 1264 and is already ramped up at both the D1D Fab in Hillsboro, Oregon, and in Fab 12C located in Chandler, Arizona. In addition to these, Fab 24E in Leixlip, Ireland, is going to complement the manufacturing resources and Fab D1C in Hillsboro finally is also undergoing a major transition to 65 nm in 2006. This one, by the way, was Intel's first manufacturing facility to utilize 300 mm wafers. All fabs we listed are producing based on large 300 mm diameters today.

The introduction of the Merom design will be a turning point in Intel's product policy, because it will be the backbone for all processor families that go into the desktop, the mobile or the enterprise space. In contrast, the desktop and enterprise markets are provided with Pentium 4 and Pentium D NetBurst architecture processors while the mobility CPUs are derived from the more efficient Pentium M design. At this point we should also mention that all processors currently shipping out of AMD's Fab 35 facility in Dresden, Germany, are already based on one single processor design. Still AMD has not yet been able to transition to neither a 65 nm production process or 300 mm wafer manufacturing.