Two Xeon CPUs Are Better Than One Intel P4 Extreme Platform

Memory Of Up To 16 GB

Because the Intel E7505 chipset always synchronizes the processor data bus with the main memory (1:1), only DDR266 memory is suitable for such a platform. As with the 875, the chipset has a dual memory controller, with which it can attain a theoretical memory performance of up to 4.2 GB per second at 133 MHz. For comparison purposes : The 875 chipset manages 6.4 GB per second on the basis of its higher speed of 200 MHz. System security, however, plays a bigger role, and that’s why Intel integrates the ECC (Error Checking and Correction) option.

Upgrade : ECC Requires An Additional Chip Per Row

Like the 875 chipset, the E7505 manages 8 rows (also called pages). Reminder : 1 memory module has either one row (single page) or two rows (double page). The following table provides a sample calculation for the respective maximum memory upgrade of the platforms (without ECC) :

Swipe to scroll horizontally
Memory expansionModuletypical structure (non-ECC)
1 GB24 Rows x 8 Chips x 256 MBit = 8,192 MBit
2 GB48 Rows x 8 Chips x 256 MBit = 16,384 MBit
4 GB48 Rows x 8 Chips x 512 MBit = 32,796 MBit
8 GB48 Rows x 16 Chips x 512 MBit = 65,536 MBit
16 GB48 Rows x 16 Chips x 1 GBit = 131,072 MBit

However, if the user wants to play it safe and use modules with ECC, then he should note that an additional chip would have to be added per row. This chip is merely responsible for the proof totals and does not have any influence on the maximum memory upgrade.

Swipe to scroll horizontally
Number of possible chips without ECCNumber of possible chips with ECC

Memory from Corsair with CL 2.0-3-2-6 timings

Registered and ECC memory from Mushkin with CL 2.0-3-2 timings

Registered and ECC memory from Legacy Electronics with CL 2.5 timings

DDR333 Registered and ECC memory from Infineon with CL 2.5 timings

To give you a worst case example : Modules with 16 GB ECC system memory can consist of 144 chips - an enormous burden for the Memory Controller Hub ! However, only 128 of these chips are used for actual memory functions, while the rest is used for administrative tasks.

Registered Versus Unbuffered Memory

Classical memory is always available in unbuffered versions. What’s new is registered memory (previously referred to as buffered memory). The more chips a memory controller has to manage, the less clear the data signals will be.

And now the trick : If you put a small manager in front of the nose of individual memory chips, every row/page will trick the memory controller into believing that only one chip is available. And this improves the signal quality and data security. But this comes at the cost of speed because the small register chip causes a short time delay in the electrical signals.

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