SiPearl this week signed a deal with Open-Silicon Research, a contract developer of chips, and announced some additional details about its upcoming Rhea system-on-chip (SoC) for high-performance computing (HPC) applications. The new processor will be ready by 2023.
Under the terms of the deal, Open-Silicon Research, the India based entity of OpenFive, will provide physical design services to SiPearl. Typically, such services include integrated circuit layout, design verification, layout post processing, and tapeout. In addition, Open-Silicon Research will also be responsible for implementation of Rhea's HBM2E memory subsystem, 2.5D packaging, chip bring up, and ramp up to volume production.
SiPearl will use TSMC's N6 fabrication technology with several EUV layers for the Rhea. The Franko-German company expects to ship its Rhea SoC in the fourth quarter of 2022, though it is unclear when the first European exascale supercomputer powered by Rhea will be available.
It may seem ironic, but SiPearl's Rhea SoC, which is designed to ensure Europe’s supercomputer sovereignty, will be implemented in India and produced in Taiwan.
SiPearl has not formally announced specifications of its Rhea SoC, but general characteristics of the processor leaked last year when a French politician visited the company. Based on preliminary information, the top-of-the-range version of the Rhea SoC will feature 72 Arm Neoverse Zeus cores interconnected using a mesh network, 68 mesh network L3 cache slices, and various additional IP blocks.
One of the most impressive features of the SiPearl Rhea is its hybrid memory subsystem comprising four HBM2Ememory stacks as well as four or six regular DDR5 memory channels. Such a DRAM subsystem will combine a very high bandwidth provided by HBM2E and a very high capacity enabled by DDR5 memory modules.
Based on what we know about capabilities of already announced HBM2E devices and viable DDR5 memory modules that will be available in 2022, a Rhea SoC could feature up to 96 GB of HBM2E at 1.6TB/s as well as up to 6TB (using 8-Hi 16Gb-based DDR5 stacks) or 12TB (using 16-Hi 16Gb or 8-Hi 32Gb-based stacks) of DDR5 memory using two modules per channel. Keep in mind though that this is our speculation at this point.
"We highly regard our partnership with Open-Silicon Research, and we are excited to utilize the company's experience implementing very large deep-submicron custom silicon designs, together with their global supply chain management track record shipping production volumes, to deliver this highly complex 6nm SoC solution with differentiated HBM2E IP in a highly advanced 2.5D package," said Philippe Notton, Founder of SiPearl. "We are confident that this partnership will enable vast opportunities to develop new HPC applications with our mutual customers."