L2 Cache Management In Alpha Processors
At first glance, the AMD architecture seems to be inferior; since each core has its own L2 cache, the two caches must synchronize their work, a process that costs time and performance. AMD has apparently adopted the cache management of the Alpha processor, however, which allows a core to query the status of a cache cell of the other core over the snoop channel without slowing down the remaining data transfer.
In any case, fewer transistors consume less power. The L2 cache of the Turion 64 X2 is only half or a quarter of the size of the Core Duo cache, so the power consumption of AMD's dual core is only slightly higher than that of the mobile Intel competitor, if at all. The reason why power consumption may be higher is that, according to Intel, unused parts of the L2 cache are disabled, which should cut power usage considerably. After all, the cache alone accounts for fifty-odd percent of the entire die surface of the processor, and power consumption is a function of the number of transistors used.
The high surface area of the L2 cache surely is the reason why the L2 cache of the Turion 64 X2 processors, with a maximum of 2 x 512 kB, could not be larger when compared to the single-core Turion 64 models. Unlike Intel's Core Duo processors, the cache is relatively small, because the 90 nm manufacturing technology simply does not allow for more on the small die surface. In contrast, Intel has been using 65 nm process technology for its processors for quite some time, and can therefore fit far more transistors on the same chip surface.
The benchmark results show which of the two cache architectures is superior in real-life conditions.
Multi-core Power Management
To make sure that the second core only consumes power when it is active, a multi-core processor like Turion 64 X2 needs a much more complex power-saving technology.
AMD puts "multi-core power management" to use in handling this issue. In greatly simplified terms, this refers to the proven power-saving mechanism Powernow, applied to two cores. When one of the cores is inactive, it reduces its clock rate to a minimum of 800 MHz and its feed voltage to 1.075 V, dozing along while the other core does its job. The clock rate and supply voltage of the second core depend on the load generated by the applications running.
Multi-core power management and energy states of the Turion 64 X2
The interaction of the CPU, operating system and applications is controlled by the Advanced Configuration and Power Interface (ACPI), which is embedded in the operating system and in special drivers that work with the components. For example, a CPU driver running on the ACPI makes sure that the CPU can continuously report the load level to the operating system and automatically enter various energy states (referred to as P-states) characterized by two variables: supply voltage and clock rate.
Interestingly, a Turion 64 X2 core can operate at the minimum clock rate (i.e., enter the lowest P-state) while the other core reduces its power consumption even further by entering the C1 state via a halt command. In this state, the chipset is disabled, but the core's own registers and caches remain active.
Even more power can be saved if the processor enters the C2, C3, or C4 states. These states are therefore especially important for laptop processors. AMD's dual-core laptop processor supports these states, which is another benefit of the Turion 64 X2 processor. However, as in real life, a deep sleep results in somewhat extended wake-up times. In other words, it takes longer for a processor to be reactivated from the C2 state than from the C4 state, even though the user may not notice this wake-up delay.
