RISC V: The Open Standard Architecture
Latest about RISC V

New Emulator Lets Some x86-64 Games Run on RISC-V Dev Board
By Anton Shilov published
StarFive's VisionFive 2 board can now run select x86-64 games with Box64 0.2.4 emulator.

Loongson: Next-Gen Quad-Core Chinese CPU Matches Intel's Tiger Lake
By Anton Shilov published
Loongson publishes test results of its quad-core 3A6000 processor at 2.50 GHz.

BeagleBoard Announce RISC-V Powered BeagleV-Ahead
By Les Pounder published
After a delay caused by a pandemic and global supply chain issues, BeagleBoard unleash its latest Beagle.

Chinese Researchers Used AI to Design RISC-V CPU in Under 5 Hours
By Mark Tyson published
A wholly AI-designed RISC-V CPU was created from scratch in five hours and booted Linux, performing on par with an i486.

Loongson to Double Thread Count on Next-Gen 3A6000 CPUs
By Anton Shilov published
Loongsom enables SMT for its upcoming 3A6000 processors in Linux.

Newly Revealed RISC-V Vector Unit Could Be Used for AI, HPC, GPU Applications
By Anton Shilov published
Semidynamics unveils fully customizable RISC-V vector unit.

Milk-V Unveils RISC-V Raspberry Pi Alternative: Milk-V Mars
By Les Pounder published
The middle board in a trio of RISC-V Raspberry Pi alternatives finally gets a name and a spec sheet, but no price.

Loongson Begins to Enable CPUs That Could Rival AMD and Intel Offerings
By Anton Shilov published
Loongson has started posting its first Linux patches for the upcoming 3A6000-series processors, which promise to rival AMD's Zen 3-based CPUs.
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