RISC V: The Open Standard Architecture
Latest about RISC V

By Aaron Klotz Published
XSi has created a new RISC-V microprocessing chip architecture that combines a RISC-V CPU core with vector capabilities and GPU acceleration into a single chip.

By Zhiye Liu Published
Yingren (aka InnoGrit) has announced the YRS820, a high-end PCIe 5.0 controller for consumer SSDs based on the RISC-V architecture.

By Anton Shilov Published
Alibaba continues to flex its RISC-V muscle, expects to roll-out datacenter-grade RISC-V CPU this year.

By Anton Shilov Published
SiFive's optimistic outlook may point to new RISC-V licensing deal with Google.

By Christopher Harper Published
India launches a RISC-V powered Aries v3.0 development board for roughly the equivalent of $20 USD. It's powered by a 32-bit, 100 MHz CPU with 256KB of SRAM.

By Anton Shilov Published
Loongson tapes out the 16-core/32-thread LS 3C6000 CPU, preps 32-core and 64-core processors.

By Anton Shilov Published
Chinese Academy of Sciences builds 256-core Zhejiang 'Big Chip,' looking towards wafer-scale chips .

By Matthew Connatser Published
Qualcomm and four other semiconductor companies have jointly formed Quintauris, which is dedicated to enabling next-generation RISC-V hardware development.
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