AMD Zen 6 CPUs Are Reportedly Based On The 2nm Process Node

Ryzen CPU
Ryzen CPU (Image credit: AMD)

A purported AMD engineer's LinkedIn profile has exposed the codename and process node for AMD's distant Zen 6 processors. Zen 5, which should hit the market by 2024, is the next microarchitecture up to bat, so there's still a long way to go before we see any glimpse of Zen 6.

The new information comes courtesy of Md Zaheer, who appears to be a senior silicon design engineer at AMD that has worked on the power management aspect of Zen 4, Zen 5, and Zen 6 processors. The person has since disguised the names of the AMD projects he has worked on, but Twitter user Maraux David took a screenshot of the original description before the changes. Admittedly, it's not a big blunder since AMD has already revealed some details about Zen 5. However, it does provide some information on Zen 6.

Zhiye Liu
News Editor, RAM Reviewer & SSD Technician

Zhiye Liu is a news editor, memory reviewer, and SSD tester at Tom’s Hardware. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.

  • thisisaname
    Zen 7 will blow your mind!
    Reply
  • drivinfast247
    thisisaname said:
    Zen 7 will blow your mind!
    Zen 8 will warp your perception of reality.
    Reply
  • NWCherokee
    rnso4nfdM9wView: https://www.youtube.com/watch?v=rnso4nfdM9w
    Reply
  • The Historical Fidelity
    I whole heartedly disagree with the writer’s claim that zen 5c is similar to Intel e-cores. Zen 5c is a density optimized version of zen 5 with 1/2 L3 cache that utilizes simultaneous multi-threading. Nothing like the Intel e- cores.
    Reply
  • Alvar "Miles" Udell
    Who would have thought that a processor successor to a 3nm one is a 2nm one!?
    Reply
  • DaveLTX
    The Historical Fidelity said:
    I whole heartedly disagree with the writer’s claim that zen 5c is similar to Intel e-cores. Zen 5c is a density optimized version of zen 5 with 1/2 L3 cache that utilizes simultaneous multi-threading. Nothing like the Intel e- cores.

    And on top of that, it is fully ISA compatible with Zen 5 down to having AVX512 still.
    Unlike gracemont or whatever mont they're following up with
    Reply
  • DaveLTX
    Alvar Miles Udell said:
    Who would have thought that a processor successor to a 3nm one is a 2nm one!?
    oh you do if your name is Intel! :ROFLMAO:
    Reply
  • Amdlova
    Amd milking way... one launch per year, same product but with 5% increase performance. New bugs... "Pay more for the bugs of tomorrow".
    Reply
  • TerryLaze
    The Historical Fidelity said:
    I whole heartedly disagree with the writer’s claim that zen 5c is similar to Intel e-cores. Zen 5c is a density optimized version of zen 5 with 1/2 L3 cache that utilizes simultaneous multi-threading. Nothing like the Intel e- cores.
    DaveLTX said:
    And on top of that, it is fully ISA compatible with Zen 5 down to having AVX512 still.
    Unlike gracemont or whatever mont they're following up with
    Which makes one question, why do they even bother at all?!
    If they only have less cache then the only thing that they could possibly do is be slower than the normal cores while still using pretty much the same amount of power...
    Reply
  • Neilbob
    Amdlova said:
    Amd milking way... one launch per year, same product but with 5% increase performance. New bugs... "Pay more for the bugs of tomorrow".

    Where do you come up with the nonsense you so often post? I genuinely wonder. Or are you just being a parody of a troll or something?

    None of the Ryzen launches (Zen+ notwithstanding) have had performance increases as low as 5%, and every bit of information we've had about forthcoming products doesn't suggest otherwise.

    And one product per year or 18 months feels like a decent launch cadence to me. I'd be annoyed to buy the 'latest, greatest thing' from one certain company only to have it totally superseded about 6 months later.

    As for bugs, of course there are some of those. Intel has them too. They're often called errata.
    Reply