SSE 4.2 And The Technical Nitty-Gritty
SSE 4—Complete at Last
With the switch to its 45 nm production process, Intel introduced SSE4.1 into the Core 2 processors. As the ".1" implies, this was only the first iteration of the SSE4 instruction set, and was not yet fully complete. Now, Nehalem comes with the full complement of instructions enabled. Specifically, SSE4.2 adds seven new commands: CRC32, PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM, PCMPGTQ, and POPCNT.
The following table compares the technical specifications of the Core i7, Core 2 and AMD Phenom processor families.
Feature | AMDPhenom | IntelCore i7 | IntelCore 2 |
---|---|---|---|
Core | AgenaToliman | Bloomfield | Yorkfield / XEWolfdaleKentsfield / XEConroe / XE / 2048Allendale |
Production Process | 65 nm | 45 nm | 65 nm45 nm |
Max. Frequency | 2.80 GHz | 3.20 GHz | 3.20 GHz |
L1 Cache | 64 + 64 KB | 32 + 32 KB | 32 + 32 KB |
L2 Cache | 512 KB | 256 KB | 4 MB |
L3 Cache | 2 MB | 8 MB | - |
Max. Thermal Loss (TDP) | 140 W | 130 W | 136 W |
CPU<->Northbridge | HyperTransport | QuickPath Interconnect | Front Side Bus |
CPU<->CPU | HyperTransport | QuickPath Interconnect | Northbridge internal |
Max. Core Speed | 3.20 GHz (25.6 GB/s) | 6.4 GT/s (12.8 GB/s) | 400 MHz (12.8 GB/s) |
Min. Core Speed | 800 MHz (6.4 GB/s) | 4.8 GT/s (9.0 GB/s) | 200 MHz (6.4 GB/s) |
FSB (internal) | 200 MHz | 133 MHz | 400 MHz333 MHz266 MHz200 MHz |
64-Bit | x86-64 | EM64T | EM64T |
Hyper-Threading | - | yes | - |
MultimediaExtensions | MMX3DNow!SSESSE2SSE3SSE4.1 | MMXSSESSE2SSE3SSSE3SSE4.1SSE4.2 | MMXSSESSE2SSE3SSSE3SSE4.1 |
Virtualization | Pacifica | VT | VT |
Power Saving | Cool‘n’Quiet 2 | Enhanced Halt State (C1E)SpeedStep | Enhanced Halt State (C1E)SpeedStep |
Thermal Protection | Thermal Diode | Thermal Monitor 2 | Thermal Monitor 2 |
SpeedStep | no | yes | yes |
Execution Protection | XD bit | XD bit | XD bit |
TrustedExecution | Presidio | LaGrande Technology | LaGrande Technology |
Active Management | no | iAMT2 (V-Pro) | iAMT2 (V-Pro) |