Today we're sorting out what's happened with Intel and Micron's 3D XPoint collaboration since it was announced in late July.
The Stage Is Set
All is quiet on the non-volatile memory front these last few weeks. Intel-Micron dropped the 3D XPoint bomb in late July, which led to anticipation and speculation prior to the Flash Memory Summit. FMS proved to be a hotbed of speculation, which led to more anticipation ahead of the Intel's Developer Forum (IDF), which led to a great deal of talk, but very little new information.
Looking back, some nuances emerged, some details were clarified and some answers shrunk further into obscurity. We'll try to pick through what we heard, what we know and even what we don't know in an attempt to provide some closure before products begin to show up, or more details slip and slide into our hands.
Everyone seems to agree that 3D XPoint will be the sliced bread of 2016 and beyond, but nobody seems to know if we’re talking Ciabatta or Focaccia (to butcher the analogy).
Intel put its NVM solutions group GM Robert Crooke on stage at IDF with Al Fazio, an Intel fellow. Together they deftly dodged every detailed, how-it-works question tossed their way, leaving some audience members visibly bewildered. Geof Findley, Intel’s Director of Memory Ecosystems, practically dared his audience to ask questions about 3D XPoint, and himself to answer them; he half cringed, half laughed when he got to that small section of his presentation (on memory).
We also had a chance to chat with Crooke one-on-one. What follows is a summary of what we learned and what we didn't, along with a few tidbits that go beyond the singular topic of 3D XPoint (pronounced 3D cross-point).
Here was our original piece the day of the Intel-Micron joint announcement. Back then, we learned the structure of 3D XPoint, we saw the models and we heard the explanation. Simply put, 3D XPoint is an intermediary storage layer between NAND and DRAM that offers 1000 times more speed and endurance than NAND along with 10 times the density of DRAM. To top it off, it is persistent, meaning it doesn't lose data when power is removed.
At FMS, we actually saw someone use their arms to re-create the 3D XPoint model (the one in the picture above) in a pantomimed form of solo Twister. One arm was the word line, the other the bit line, and the presenter made his head the memory cell. You get the picture (we didn’t have the foresight to have a camera ready for such a spectacle).
At IDF, Intel had a gigantic 3D model on stage. We learned during the original announcement that Intel is building its first 3D XPoint iteration on the 20nm process with a 128Gb die density, and that there will initially be two layers. The technology could be scaled by stacking layers higher, and eventually by shrinking lithography.
We learned that 3D XPoint used a bulk material property change (rather than a stored charge) to address each cell. This provides a level of granularity we haven’t seen before, and subsequently offers better scalability and higher performance. However, we didn’t learn what that material change process would be.
New Details From IDF
One thing Intel formally announced at IDF was the 3D XPoint product branding, specifically on the storage side—that is, a 3D XPoint device that presents itself as block storage. The products that will emerge with the Optane branding will not only use 3D XPoint, but will come with optimized controllers, interfaces and software. Those products will come in the SSD form factors, namely add-in cards (AIC), M.2 and U.2 flavors.
Intel left out a few details, which drew the bewildered looks and baffled questions, but we’ll address them in the next section.
Our initial thought was that Intel would target enterprise applications, like in-memory databases and big data. During IDF, Intel CEO Brian Krzanich, Crooke and Fazio continued to talk about these applications, particularly giving examples like advanced fraud detection and algorithmic financial trading.
However, this time around, Intel also made a point of talking about its applicability in games and professional workloads like 4K video editing. For gaming, Crooke talked about the ability to load bigger portions of games in a 3D XPoint scenario, thus eliminating the need for developers and players to break or load games in levels.
What We Still Don’t Know
How It Actually Works
Which is to say, what is the bulk property change technology in play?
In a sit-down chat with Crooke during IDF, we asked him three different ways what technology 3D XPoint was using. His first answer was simply that it was new and it is 3D XPoint. He also wondered why everyone was so focused on the property change mechanism (some have said PCM, some ReRAM), saying, "it’s recreational to some extent how we’re accomplishing that." His third reply was simply that it was a competitive advantage, meaning we won’t know until it is impossible for Intel to keep it from us.
Given that Intel’s SSD market share is a fraction of Samsung’s, even with Micron’s share thrown on top, we suppose it’s understandable. Intel isn't accustomed to playing second fiddle. According to TrendFocus, Intel continues to dominate the enterprise PCIe market, but Samsung has a monstrous lead in total exabyte output and units sold.
Even details from Micron's latest Analyst Conference do little to clarify the type of memory employed in 3D XPoint. At any given time, the company has up to 26 different memory technologies under evaluation.
Speaking of Samsung, a presentation from 2012 referenced the idea of using what the company termed a “3D Cross-point ReRAM” architecture, and called into question its long-term scalability. Samsung was suggesting at the time that a Vertical ReRAM (VRRAM) architecture would be more effective and scalable in the long term, whereas ReRAM-based "3D x-point" would only be a temporary solution.
In other words, this architecture is not new, and in fact Samsung rejected it because the company didn't think it had longevity, at least according to that presentation. However, Crooke thinks it does, and addressed 3D XPoint scalability by pointing out that the lithography issues are pretty simple to solve with this architecture, and that Intel can add more layers, but can also bring the pillars closer together.
DIMMs And JEDEC Compliance
One new item Crooke revealed on stage at IDF was that 3D XPoint would ship in memory-mapped devices (DIMMs). We asked him whether they'd be JEDEC-compliant and he replied they'd be compatible with DDR4 mechanically and electrically, but that the technology would require a new interface since it is non-volatile, and that Intel was integrating it into its platforms.
An audience member asked Geof Findley, Intel's memory ecosystem director, "Is the protocol for 3D XPoint going to be identical to DDR4 DRAM?" Findley answered evasively: "It will plug into a DDR4 socket. Next question."
When asked if it was an NVDIMM by JEDEC standards, Findley answered, simply, "No." When asked if it will leverage a proprietary protocol that would remain proprietary to Intel, he answered, simply, "Yes." Moreover, when asked again whether it would be JEDEC-compliant, he replied, "Not at this time."
There are your answers, delivered with dental forceps.
It appears the specter of a proprietary interface looms menacingly on the horizon, which is fomenting a dire sense of foreboding in the industry. During a recent standing room-only presentation at the Flash Memory Summit, the mere mention of the requirement for a proprietary interface cast a pall over the audience. Such an outcome could hamper adoption and put quite a bit of unbridled power in the hands of Intel and Micron. Intel already has a great deal of control at the CPU and chipset level due to a lack of competitors.
Findley clarified that the 3D XPoint support would only be applicable to a future Xeon processor. He specifically stated that support was not due on the Grantley refresh, but rather the following generation.
Will performance and cost be closer to DRAM or NAND?
Intel tossed around some high-level figures, but was not specific. There was no discussion about pricing, even on a percentage basis.
SRAM is the baseline in the chart above. As you can see, among other things, the capacity points will be the same as NAND, but offer a 1000x performance increase when measured solely in latency.
Intel has been a staunch proponent of the new NVMe (Non-Volatile Memory Express) protocol, a lightweight register interface constructed from the ground up with future non-volatile memory technologies in mind (not NAND).
In fact, Intel established the NVMe standards committee, which consists of every major memory manufacturer. Intel recently revealed that it founded the NVMe development committee specifically with the goal to provide a refined interface to empower 3D XPoint-based products. Yes: In an odd twist of fate, Intel’s own competitors helped pour fuel onto the 3D XPoint fire.
The interface is the key; connecting 3D XPoint via the NVMe interface brings a 10x reduction in latency compared to a standard NAND-based NVMe SSD. Utilizing other protocols, such as AHCI or SCSI, would saturate the CPU with computational overhead long before the system reaped the latency and performance rewards of the underlying medium.
Other Things We’ve Wondered About…
Floating Gate vs CTF
One of the things we recently learned from Micron was that charge trap flash technology (which most NAND manufacturers are moving to for 3D NAND) has endurance limitations due to charge spreading. Micron indicated that Floating Gate technology isn’t as susceptible to rapid charge loss, and that CTF increases in complexity during 3D NAND scaling. We wanted to hear this directly from Intel.
Crooke said that floating gate technology has been the foundation of NAND for 20 years, and IMFT understands the physics very well due to its extensive familiarity with floating gate technology.
3D NAND allowed IMFT to take a step back to a larger process, and instead increase the density via vertical stacking. This allows for bigger floating gates. 3D floating gates are difficult to engineer, but they still offer more robust endurance characteristics.
On the other hand, charge trap technology suffers from leakage at higher densities. The cells aren’t as discretely isolated as they are with floating gate, so CTF is susceptible to charge dispersal and interference across cells. Crooke made an analogy to a strip of cloth that is a continuous sheet of nitride, and putting oil dots on it. The dot is contained in one spot at first, but over time, the oil disperses.
Intel is all about solving the hard challenges, Crooke bragged, so it is sticking with floating gate. He said that the company’s first 3D NAND product would be the world’s first 256Gb 3D MLC NAND, and its TLC product will extend density to an unheard-of 384Gb.
QLC (Four-Bit MLC)
Quad-level cell is the next natural progression to increase the density of NAND, and this technology would prove to be very efficient when utilized in tandem with 3D XPoint caching in a hybrid implementation. 3D XPoint would be a natural type of super-fast cache front end for a massive low-endurance (and low-cost) QLC SSD data store.
When I asked Crooke about whether Intel was developing this type of implementation, he gave a knee-jerk, enthusiastic “Yes!" before throttling back down and indicating that everyone in the industry is merely thinking about it and researching it. First it would have to work.
TLC 3D NAND
Samsung has been busy with data center SSDs featuring its 3D TLC V-NAND. In fact, every one of its new enterprise SSDs (which it announced at the Flash Memory Summit 2015) utilize 3D TLC NAND. During a question and answer session at FMS, Ryan Smith, the Director of NAND Marketing at Samsung Semiconductor, indicated that TLC is the “killer” application for 3D NAND, and Samsung foresees it taking over every single vertical.
Crooke would not pre-announce anything, of course, but he did say Intel has some exciting 3D NAND products coming. We recently reported our discovery of Intel’s (apparently) pending DC P3520 Series. The DC P3520 appears to be an Intel NVMe controller paired with 32-layer IMTF 3D NAND.
DRAM/NAND Market Impact
Surprisingly, during Micron's Summer Analyst Conference, CEO Mark Durcan indicated that 3D XPoint could equate to almost half of Micron's DRAM business in 2018, saying: "In terms of how quickly will this market grow and how quickly we’ll become significant, I think that is hard to know exactly today...the 2018 timeframe could easily be of the same order of magnitude as our DRAM businesses in that timeframe. So maybe not the same size, maybe half the size in 2018, but it will be a significant additive revenue stream to Micron at the time."
Durcan could be referring to the revenue 3D XPoint generates, or he could be referencing the bit output, which leaves his statement open to interpretation. In either case, Durcan is indicating 3D XPoint will be comparable to Micron’s $40+ billion DRAM business in two short years. This is an incredibly bullish statement, and it is hard to imagine that amount of production will not affect the DRAM or NAND segments.
The DRAM and NAND markets serve as an oasis of stability for Micron, and both it and Intel have gone to great pains to assuage skittish investors by indicating that 3D Xpoint will not cannibalize DRAM or NAND markets, but will be additive. This, too, is quite optimistic, and it would be more realistic to imagine it eating into a little of both.
The more interesting side effects of 3D XPoint will likely come from IMFT’s competition. Samsung, in particular, is in a nice spot to flood the market with either of the opposing NAND or DRAM mediums. It is in the process of building a $23 billion fab that will be operational by 2017, and that, by some estimates, is large enough to equal the 300mm wafer production of SK Hynix and SanDisk combined.
Samsung isn’t commenting on what its "superfab" will be used for, but it can pump out either NAND or DRAM. If Samsung chooses to flood the market with cheap NAND on one end and cheap DRAM on the opposite end, it can create enough price pressure to relegate 3D XPoint to niche applications, at least until Samsung is ready to roll out its competing technology.
Cue the return of the zero-margin DRAM market endured by the memory manufacturers over the last decade. Admittedly, this would be a bit of a nuclear option for Samsung, as it would also pay dearly in margins, but the key takeaway is that the company has the option of pushing the red button.
SK Hynix also recently announced it is investing $38.9 billion for three semiconductor fabs, so the attacks could come from multiple angles. Another possibility is that IMFT’s competitors could embrace, or create, an industry standard protocol for their own non-volatile products, which would fly in the face of Intel's proprietary interconnects.
Back To Square One
A few final notes. We’re obviously anxious to see 3D XPoint in action, and to tell you more about it. We’ll keep pursuing both ends, but it will undoubtedly be a while. Intel and Micron are walking a very interesting and fine line here.
One of the best things Intel did at IDF was to repeat the mantra that 3D XPoint is both bigger memory and faster storage. It doesn’t really unmuddle its future, but it says more exactly what it is—low-latency storage and high-capacity DRAM. Just how far Intel and Micron push the boundaries of latency and capacity will determine how additive or substitutive it will be to the lucrative NAND and DRAM products.
During Micron's winter analyst meeting earlier this year the company showed slides pointing to a 2015/2016 Memory A and a 2017/2018 Memory B. Micron is vocally positioning "Memory B" as its high-performance non-volatile memory product.
When pressed, Crooke claimed not to know anything about a Gen 2 or Memory B, but it’s there clear as day. Either Crooke is being coy, or Intel isn't invested in the forthcoming Memory B. The plot thickens.
At Micron's follow-on Summer Analyst Conference it presented an updated chart that also details the emergence of Memory B, but this time listed as "EM Gen 1" (Emerging Memory). This new form of memory will come after IMFT is already rolling second-generation 3D XPoint.
Every unearthed detail only uncovers more questions, further highlighting how little we actually know about IMFTs 3D XPoint.
In the media we feast on the bafflement and bewilderment, so these are exciting times. I take my sliced bread toasted, with butter and jam...
Fritz Nelson is the Editor-In-Chief of Tom's Hardware.