The Mother of All CPU Charts Part 1

Socket 775: June 2004 To Today (UPDATED)

Intel took a big step in the transition from Socket 478 to Socket LGA775. The abbreviation LGA stands for Land Grid Array and thus makes clear that the pins of the CPU have moved to the socket, which was Intel's way of shifting the pin problem to motherboard manufacturers. At the same time, the manufacturer presents the chipsets 915 and 925X. In addition to DDR2 modules, the 915 also supports conventional DDR memory. The new socket set another heat loss record for Intel: with the 3.8 GHz CPU, a real heat loss of 104 watts was reached, one that we measured several times in the THG lab. From the point of view of design, the processor is designed for a maximum heat loss of 115 watts (TDP 115).

AMD set the example - Intel followed it: the introduction of a new model numbering scheme that ultimately obscures the reference to the clock speed. But the intention is clear: competing with AMD, Intel is using the model numbering system in an attempt to artificially raise performance indications for the customer. Thus, for example, the Celeron is assigned numbers in the 300s, while the Pentium 4 gets numbers in the 500s. Does that mean the 600s are coming soon?

The Pentium 4 Extreme Edition 3.4 GHz also introduced for this socket is still based on the old Gallatin core. It manages to stand out slightly in a few benchmarks from the Pentium 4 with 3.8 GHz, which also has SSE3, taking the latter CPU to absurd proportions. Intel was planning a Pentium 4 with 4 GHz, but withdrew it. Our tests ultimately showed that even the 3.6 GHz version with the boxed cooler has problems with high heat loss. Increasing the FSB to 266 MHz (1066 QDR), which was the whole reason Intel released a new 925XE chipset, did not give the Pentium 4 Extreme Edition and notable boost in performance. Here it is obvious that the architecture has reached its limit.

Even for the LGA775 platform, there is once again a Celeron with the D abbreviation, available with 133 MHz FSB and a 256 kB L2 cache.