Extreme Overclocking: 10 Ryzen CPUs Under LN2

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OC: Ryzen 7 1800X

Since we have multiple Ryzen 7 1800X CPUs, each one gets its own number. Our freshly lapped processor is first.

Ryzen 7 1800X #1: 5411 MHz

The temperature drops, frequencies increase, but our optimism does not last for long. This CPU wouldn't stabilize at 5420 MHz, and it's just barely able to run at 5400 MHz. With a little work, and by tweaking the settings, we manage to pass GPUPI at 5411 MHz, reducing the three-second delta to just 0.9s.

We score a beautiful 2430 points in CineBench R15 at 5323 MHz, again falling short of first place. Our CPU is a good one, but it isn't setting any records.

Before moving on to other samples, we make note that this chip's IMC is quite average. Under LN2 cooling, it's impossible to push our memory beyond 3000 MT/s. Unable to achieve higher data rates, we instead tighten timings to 11-11-11-26 and use a REF_CLOCK setting of 139 MHz to boost our score a bit.

Ryzen 7 1800X #2: 5200 MHz, DDR4 At 3310 MT/s

Our second sample isn't quite as good as the first one. As a result, we didn't spend a lot of time trying to push its performance. After assembling and waterproofing our platform, we spent another two hours toying with the chip's limits. In the end, Cinebench ran successfully at a little higher than 5200 MHz.

Incidentally, this CPU's memory controller is quite good. It allowed us to complete SuperPI 32M with a memory frequency of 1655 MHz (3310 MT/s).


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Jean Michel "Wizerty" Tisserand
Jean-Michel "Wizerty" Tisserand is a French extreme overclocker, and former OC world champion. Passionate and curious, he's always into pushing hardware to its limits. Willing to transmit his knowledge, he created the French Overclocking Federation, and writes merciless hardware torture articles!
32 Comments Comment from the forums
  • InvalidError
    It isn't surprising that the highest-end CPUs have the highest and least troublesome overclocks as that's what chip binning is for - the best dies go to the premium SKUs first, lower tiers get what is left over.
    Reply
  • -Fran-
    19937674 said:
    It isn't surprising that the highest-end CPUs have the highest and least troublesome overclocks as that's what chip binning is for - the best dies go to the premium SKUs first, lower tiers get what is left over.

    Even more, it's very interesting since it gives some credibility that AMD is not binning due to defects, but electrical properties, hence, making the rumour mill of being able to unlock some 4C and 6C to higher core counts not that far-fetched.

    Cheers!
    Reply
  • Wisecracker
    Très bon!
    (hope I used this correctly)

    Just wondering ... would it be considered a 'faux pas' (or, an insult to AMD) to release the batch numbers?

    Reply
  • theyeti87
    19937697 said:
    19937674 said:
    It isn't surprising that the highest-end CPUs have the highest and least troublesome overclocks as that's what chip binning is for - the best dies go to the premium SKUs first, lower tiers get what is left over.

    Even more, it's very interesting since it gives some credibility that AMD is not binning due to defects, but electrical properties, hence, making the rumour mill of being able to unlock some 4C and 6C to higher core counts not that far-fetched.

    Cheers!

    Wasn't that a similar case with the Phenom X4, X3, and X2's? Or were those 3's and 2's disabled cores due to defect?
    Reply
  • -Fran-
    19937706 said:
    19937697 said:
    19937674 said:
    It isn't surprising that the highest-end CPUs have the highest and least troublesome overclocks as that's what chip binning is for - the best dies go to the premium SKUs first, lower tiers get what is left over.

    Even more, it's very interesting since it gives some credibility that AMD is not binning due to defects, but electrical properties, hence, making the rumour mill of being able to unlock some 4C and 6C to higher core counts not that far-fetched.

    Cheers!

    Wasn't that a similar case with the Phenom X4, X3, and X2's? Or were those 3's and 2's disabled cores due to defect?

    They were a mix of both. If you were lucky (and could track down some of the batches) you were able to unlock the CPU with little worry, but there were defective ones that when unlocked, would not work. I came across both myself.

    To be honest, I just catalog it as "interesting", because I will pay the difference to always get the full working version, but I do know there's people out there that like gambling and can track batch numbers :P

    Cheers!
    Reply
  • InvalidError
    19937697 said:
    Even more, it's very interesting since it gives some credibility that AMD is not binning due to defects, but electrical properties
    The relatively low defect rate has been a given since launch IMO: half of each CPU core is L2 cache and half of the CCX die area is the L3, so you have a 50% chance that defects within a CCX will land in L3. If the defect rate had been significant, cache defects would have forced AMD to launch models with 8MB of L3 long before the 1400.
    Reply
  • -Fran-
    19937880 said:
    19937697 said:
    Even more, it's very interesting since it gives some credibility that AMD is not binning due to defects, but electrical properties
    The relatively low defect rate has been a given since launch IMO: half of each CPU core is L2 cache and half of the CCX die area is the L3, so you have a 50% chance that defects within a CCX will land in L3. If the defect rate had been significant, cache defects would have forced AMD to launch models with 8MB of L3 long before the 1400.

    True. It's just nice to have more non-validated statistical-irrelevant proof! Haha.

    Cheers! :P
    Reply
  • Gregory_3
    This is all kind of cute, but the real market success will be played out in conventional liquid cooled and air cooled environments. Nobody is going be running high end software with condensation dripping all over.
    Reply
  • InvalidError
    19938043 said:
    Nobody is going be running high end software with condensation dripping all over.
    There wouldn't be condensation issues if OCers used the nitrogen gas boiling out of the pot to displace air and the moisture it contains around the motherboard to keep it off of it. Instead of circulating the boil-off around the motherboard though, LN2 OCers use fans to suck it away, drawing more moisture-ladden air in the area.
    Reply
  • gasaraki
    "It isn't surprising that the highest-end CPUs have the highest and least troublesome overclocks as that's what chip binning is for - the best dies go to the premium SKUs first, lower tiers get what is left over."

    While it might not be surprising, it shows the immaturity of the Ryzen processors in that the build quality is not the same between different CPUs or even CCXes and binning is what they do for the lower cored versions. If your build process was mature ALL your chips would come out mostly the same and "awesome" then at that point your forced to just shutdown cores to make the lower cored processors.
    Reply