RAM Wars: Return of the JEDEC

Measuring Modules

Figuring out how much capacity your memory module has is straightforward enough, but also involves some basic math. Arriving at the number of bits in a module involves multiplying the size of the memory chip by the number of chips in a module. For example, eight 64-Mbit chips are in a 512 Mbit module. But unfortunately, when you read module specs, module capacity is expressed in Bytes. In this case, you have to divide by 8, and are left with 64 MBytes.


DRAM that has a synchronous interface is known generically as SDRAM. This includes CDRAM (Cache DRAM), RDRAM (Rambus DRAM), ESDRAM (Enhanced SDRAM) and others.

SDRAM that meets the standards established by JEDEC (see Return of the JEDEC section) not only has a synchronous interface controlled by the system clock, it also includes a dual-bank architecture and burst mode (1 bit, 2 bit, 4 bit, 8 bit and full page). A 'mode register' that can be set at power-on and changed during operation controls the burst mode, burst type (sequential or interleave), burst length, and CAS latency (1, 2 or 3).

Just a quick note on CAS latency: CAS Latency is a performance-related timing for SDRAM that falls under the latency umbrella. This measurement is the time it takes to strobe in the Row Address, and to activate the bank. When a burst read cycle is initiated, the addresses are set up and RAS and CS (chip select) are held low on the next clock cycle (rising edge of CLK), thereby activating the sense amplifiers on the bank. A period of time equal to tRCD (RAS to CAS delay) must pass, after which CAS and CS are held low (again, at the next clock cycle). After the time period for tCAC (column access time) has passed, the first bit of data is on the output line and can be retrieved (at the next clock cycle). The basic rule is that CAS latency multiplied by the clock speed (tCLK) must be equal to or greater than tCAC (or CL x tCLK >= tCAC). This means that the column access time is the limiting factor for CAS Latency.