DRAM Performance: Latency Vs. Bandwidth
The industry is in the midst of a raging debate over DRAM performance. Today, chip makers are fighting it out, but very soon the battle zone will expand to include system manufacturers, all the way down to individual users. The debate is over bandwidth vs. latency and DRAM chip interfaces.
The PC press is scattered with inconclusive analyses about many of the contenders, including Rambus, SLDRAM, DDR SDRAM, ESDRAM, Virtual Channel and others. Only one thing is clear - Intel is pushing Rambus, and almost everyone else is looking for alternatives. Why all of the anxiety? I can only answer that with another question. "Is Rambus about performance, or is Intel merely placing another proprietary bus roadblock in the path of its competitors?"
Aside from the politics (which run very deep), the goal is supposed to be improving system performance. As these new memory types become available, users must make their own choices. In order to avoid making expensive and disappointing mistakes, it is important to understand the real performance balance between DRAM, CPUs and buses.
Do faster DRAMs make a difference?
Size is first, speed second. If your memory configuration is too small, memory page swapping to the hard disk will severely limit performance. Beyond that, the system level performance impact of faster DRAM depends on your system architecture and on what kind of applications you run.
How can the new memory types improve performance?
Only two things can impact DRAM performance - improve latency (access time) or increase peak burst bandwidth. Predictably, some of the new DRAM types improve latency, while others crank up the burst rate.
What's more important, faster latency or faster burst bandwidth?
That is the heart of the matter. As a rule of thumb for today's desktop PC, faster latency will almost always deliver a performance benefit. Increasing peak burst bandwidth sometimes offers a performance benefit, but not in every case, and not usually as much.
What happens to CPU performance when latency is improved?
When the CPU experiences a cache miss, part or all of the CPU stalls for a surprisingly long period of time. Faster latency DRAM allows the CPU to resume operation quicker. The CPU realizes this benefit each time it accesses DRAM.
What happens when peak burst bandwidth is increased?
Currently, CPUs are incapable of ingesting burst data at a rate faster than one CPU bus clock. SDRAM already satisfies this requirement. Rambus, DDR and SLDRAM pump data out in a half clock - twice as fast as the CPU can swallow it. Chip sets will have to buffer the data and slow it back down to the speed of SDRAM. Does this sound enticing?
Then why the heck does anyone want higher bandwidth?
Sometimes, the CPU must contend with master mode peripherals over DRAM. If a peripheral is busy accessing DRAM at the precise moment that the CPU stalls on a cache miss, higher bandwidth DRAM can resolve the conflict a little faster. But fast latency DRAM can achieve the same result or better depending on burst length.
Confused? Good. You need more information to make sense of all of this.
