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Platform And Process

Meet Moorestown: Intel's Atom Platform For The Next 10 Billion Devices
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Keep in mind that there are multiple families and architectures within the Atom processor family. In this article, we’re specifically focused on Moorestown and the Z-series, which is aimed at handhelds and tablets. There’s also the N-series for netbooks, the CE-series for TVs, D-series chips for entry-level desktops (D), an embedded series , and a future family “for gadgets” about which Intel wouldn’t even divulge a code-name. The ways in which these series differentiate are largely based on power profiles and performance expectations. We’re not to the point with Atom where one architecture, such as Core 2 or Core i3/5/7, applies to the entire stack. Perhaps it never will.

With Menlow, we had a platform architecture much like the classic PC design—a standalone CPU on top, with an integrated chipset below, similar to the old school northbridge and southbridge being combined into a single Platform Controller Hub (PCH). The Poulsbo chipset crammed in everything but the kitchen sink, and did it all on a relatively giant 130 nm fab process.

The architectural difference in jumping to Moorestown is massive. All that gets retained of the former chipset is the I/O complex. Memory, video, and graphics all migrate to the CPU—and not just in the package but on the actual die. Langwell uses a 65 nm process. Lincroft appears to match Silverthorne’s 45 nm process, but Intel is always careful to note that Lincroft uses a “45 nm SoC” process. It’s not the same process as before, or even a “retweaking” of it. Details here get vague.

While Intel maintains that the rest of the industry is still using 65 nm, Lincroft preserves Silverthorne’s 45 nm process. Recall that Intel’s 45 nm node was notable for its adoption of hafnium high-k dielectric technology, which got a lot of attention when it debuted in the Nehalem microarchitecture. Hafnium high-k, according to Intel, could reduce transistor-level gate leakage by over 100 times compared to the prior silicon dioxide dielectric process used with 65 nm technology. There’s more to Intel’s “LP SoC” process than hafnium, though, but engineers grew cryptic on this point. They stated that with Lincroft there was the “option of multiple transistors” as opposed to Silverthorne having “only one transistor end to end.” Then there were some furtive glances between the engineers and the press crew, and Intel would say no more on the matter. I suppose everyone is entitled to their hard-earned secret sauce.

The dimensional upshot of the Moorestown architecture is that we now have a 30% die reduction, a 40% package reduction, and a 50% motherboard reduction, reflecting significant consolidation across the platform. You’ll often see the Moorestown CPU package specified at 13.8 mm x 13.8 mm (Silverthorne was 25 mm2), but the actual die measures only 7.34 mm x 8.89 mm. One former Menlow reference design for handsets measured 75 x 148 mm. An equivalent Moorestown reference board I saw measured 69 x 130 mm, and that was with over one-third of the board surface sitting empty for an on-board battery.

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