Intel to Explore RISC-V Architecture for Zettascale Supercomputers

This week, Intel and the Barcelona Supercomputing Centre (BSC) said they would invest €400 million (around $426 million) in a laboratory that will develop RISC-V-based processors that could be used to build zettascale supercomputers. However, the lab will not focus solely on CPUs for next-generation supercomputers but also on processor uses for artificial intelligence applications and autonomous vehicles. 

The research laboratory will presumably be set up in Barcelona, Spain, and will receive €400 million from Intel and the Spanish Government over 10 years. The fundamental purpose of the joint research laboratory is to develop chips based on the open-source RISC-V instruction set architecture (ISA) that could be used for a wide range of applications, including AI accelerators, autonomous vehicles, and high-performance computing. 

The creation of the joint laboratory does not automatically mean that Intel will use RISC-V-based CPUs developed in the lab for its first-generation zettascale supercomputing platform but rather indicates that the company is willing to make additional investments in RISC-V. After all, last year, Intel tried to buy SiFive, a leading developer of RISC-V CPUs and is among the top sponsors of RISC-V International, a non-profit organization supporting the ISA.  

While around $21.3 million is a significant sum of money, Intel will be pouring a lot more into its x86-based products in the coming years, so spending on RISC-V processors does not mean a lower focus on x86 designs. On the contrary, throughout its history, Intel invested hundreds of millions in non-x86 architectures (including RISC-based i960/i860 designs in the 1980s, Arm in the 2000s, and VLIW-based IA64/Itanium in the 1990s and the 2000s). Eventually, those architectures were dropped, but technologies developed for them found their way into x86 offerings. 

With its RISC-V efforts, Intel could be killing several birds with one stone. First, suppose engineers from the joint laboratory manage to design a CPU technology that is more suitable for ZettaFLOPS-class supercomputers. In that case, Intel will be able to use it for its products. As an added bonus, Intel’s Foundry Services division will likely become a fab of choice for CPUs/SoCs developed in the joint lab. 

“High-performance computing is the key to solving the world’s most challenging problems, and we at Intel have an ambitious goal to sprint to zettascale era for HPC,” said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel. “Barcelona Supercomputing Center shares our vision for this goal, with equal emphasis on sustainability and an open approach. We are excited to partner with them to embark on this journey.” 

Last year Intel set itself an ambitious goal to build a ZettaFLOPS-class supercomputer platform by 2027, which means to increase the performance of supercomputers by 1000 times in about five years. The company said it would need new compute architectures, new system architectures, high-speed memory and I/O interfaces, novel fabrication technologies, and sophisticated chip packaging methods, among other things. One of the company’s ways to radically improve compute performance is to build an architecture that would combine the company’s x86 general-purpose cores with Xe-HPC compute GPUs. The first product that uses this concept is Falcon Shores — which is already in development.