14nm+ & Precision Boost 2
According to AMD, its 14nm+ process is denser and more power-efficient than the 14nm node it was using previously. However, the company isn't sharing much beyond those claims. To be clear, this is not the GlobalFoundries 12nm LP process that AMD will transition to in April when the Zen+ processors are expected to launch. That new process will provide even more of a performance boost over the current 14nm+ LPP FinFET.
We do know that 14nm+ enables higher frequencies at a given voltage, which AMD turns into higher base and boost clocks. The company also improved its Precision Boost 2 feature, which is comparable to Intel's multi-core Turbo Boost technology.
Precision Boost 2 is a DVFS (Dynamic Voltage Frequency Scaling) implementation designed to improve performance in multi-threaded workloads. AMD's current-gen Ryzen processors only offer dual-core or all-core boost frequencies. But the Precision Boost 2 algorithms operate on anywhere from one to eight active threads. This should help Ryzen 5 2400G capitalize on the architecture's already-strong threaded performance. AMD can also now control the frequency and voltage of each core independently (in the past, Ryzen processors could only adjust each CCX as an entire unit).
This technology should help when relatively light threads keep other cores active. These lighter threads don't utilize a given core fully, but because the core is working on something, it can still cause the processor to drop from its dual-core turbo setting into a slower all-core frequency. Game engines are notorious for this type of behavior, often running several helper threads (such as audio) on different cores.
AMD doesn't share a list of specific multi-core Precision Boost bins because the algorithm is truly opportunistic and will boost to different frequencies based upon temperature, current, and load. That isn't too surprising—Intel also stopped sharing its multi-core Turbo Boost ratios for similar reasons.
Precision Boost 2 is intricately woven into the capabilities of AMD's SenseMI suite. For instance, Pure Power uses an array of 1000 sensors to monitor all of those critical parameters, thus enabling real-time adjustments. This information flows through the Infinity Fabric. The coherent control and data interface services six different clients in the SoC, including the multimedia engines, display engine, DDR4 memory controllers, I/O and System Hub, host processing cores, and the graphics engine. AMD split the Infinity Fabric into control and data planes to optimize performance and granularity (1ms intervals) for the real-time telemetry data.
As with any product destined for mobile applications, power is key. Raven Ridge-based SoCs have the ability to shut down different blocks in order to curb consumption. The SoC also uses internal and external (on the motherboard) voltage regulators that communicate with each other, but operate independently. This allows the processor to deactivate a regulator when it isn't needed, dropping the chip into a lower power state.
Intel's Kaby Lake and AMD's Bristol Ridge processors feature two power rails, one dedicated to the CPU and another dedicated to the GPU. Raven Ridge employs a single rail for both regions to enable power sharing. This allows the SoC to dedicate more current to regions that are experiencing heavier load, purportedly boosting performance.
Shutting off areas of the chip, or power gating, requires a fast resumption time (gate exit). Simply put, if you put a core to sleep, you want it to quickly resume activity when it's called upon. AMD implemented faster resumption times to allow power gating without negatively affecting the user experience.
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