ATi's New Radeon - Smart Technology Meets Brute Force

Fill Rate, Rendering Pipelines And Triangle Size

If we look at the wireframe of the Boxster once more, we can see that some of the triangles are extremely small. In fact some triangles are so small that they build a white chaos together with other small triangles around them. You can easily understand that many of those small triangles represent one or even less than one pixel. This is an important issue for the fill rate of the pixel-rendering unit. You have to realize that the pixel-rendering unit can only be fed with one triangle at a time, unless the chip would have several T&L and triangle setup units. If the triangle consists of fewer pixels than the amount of rendering pipelines in the pixel-rendering unit, some of those pipelines will be idle. This is the big disadvantage of several parallel rendering pipelines. A chip such as NVIDIA's GeForce2 GTS that comes with four rendering pipelines will always have some idle pipelines if a triangle contains less than four pixels. Frames with many small triangles will therefore never be able to live up to the high fill rate claims. You can imagine that there are the more small triangles the lower the resolution is. This is why we can always see the effective fill rate (frame rate * screen resolution) increase as resolution increases.