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X570 Exposed: Up to Sixteen PCIe 4.0 Lanes, Flexible I/O

This is not the X470 chipset replacement you were looking for--at least according to our conversations with AMD: The X570 is not a replacement for the X470, but instead slots in as a higher tier. That means the firm’s X470 will soldier on as a value-oriented alternative to high-priced X570 models, and we may even see new X470 boards with updated layouts and features targeting people who can’t justify X570 premiums.

But this “model up” philosophy provides a reason for the firm to kill PCIe 4.0 graphics support on future X470 motherboards: Anyone who wants that pathway from the CPU to the GPU will likely be forced to buy an X570 motherboard, unless they use hacked firmware. It’s not in the firm’s interest to produce a separate AGESA for the new X470 motherboards (though we guess that this could change).

In the meantime, we spent some time over the course of several days to firm up the device connection limits for the X570 PCH, producing a block diagram from real-world application data.

The first thing most in-the-know readers will notice is that the PCH supports eight USB 3.2 Gen2 (10 Gb/s) pathways and eight SATA 6 Gb/s ports rather than four and two quoted for the CPU. That may seem odd since the X570 PCH is nothing more than a 14nm variant of the 12nm I/O die inside the Ryzen 3000-series processors, but it simply appears that the I/O die’s pathways are far more flexible than previously disclosed.

July 2nd Update: Rumors of additional USB 2.0 ports on the PCH turned out to be via conversion (breaking out the USB 2.0 data pins from the USB 3.x interface), as expected. AMD also dismissed rumors of the PCH not supporting full Gen2 transfers as an attempt by motherboard manufacturers to save cost on additional devices such as redrivers.

A little creative destruction rids the PCH version of the CPU’s memory controller and any unnecessary appendages, as each of those maximum connections must be selectively reduced by the motherboard manufacturer to fit everything into a combined 16 High-Speed Platform Lanes. That may be just as well since device bandwidth is shared over a single PCIe 4.0 x4 connection to the CPU, though we have to at least give AMD credit for doubling that over its previous PCIe 3.0 version.

(Image credit: Tom's Hardware)

We're fairly certain that the second CPU-based NVMe connection shown by AMD at its E3 Press Event should have been a breakout of the first, since motherboard manufacturers have only been able to get one PCIe 4.0 x4 NVMe interface directly from the CPU. A total of 24 CPU lanes that include 16 lanes for graphics, four for storage and four for USB 3.x Gen2 conforms to AMD's statement that "High-Speed Platform Lanes defined as the sum of GPP PCI Express lanes, SATA ports and USB ports from the chipset and processor that can be used concurrently."

Regarding the PCH, those same motherboard firms are extracting up to eight SATA ports from the PCH in addition to a second and third PCIe 4.0 x4 M.2 slots, with the only resource exclusion being that those board's third expansion card slot is disabled when the third M.2 slot is enabled. These details may explain the absence of the above image in the official slide deck AMD later provided.

We'll inspect final products to be certain about USB 2.0 count, since motherboard manufacturers occasionally double-count USB 2.0 by adding the backwards compatibility of USB 3.0 ports.

(Image credit: AMD)

Hmm, PCH, HSIO, where have we heard that before?

This article is part of the Tom's Hardware Glossary.