Seoul (Korea) - Samsung says it has developed a new "3D" package, which reduces space requirements and increases performance capabilities of today's multi-chip packages. The company plans to use the technology to improve its NAND Flash packaging starting in 2007.
Memory stacks are widely use as a solution in multi-chip packages (MCP) today as they offer semiconductor firms to bump the capacity of their chips without increasing the footprint of chips. When more and more transistors require more and more area space on a package and scaling of the production process does not provide enough real estate, the industry uses a technology called "die-stacking."
However, current stacks typically used for Flash memory or DRAM memory chips come with a performance and size penalty, as dies are not directly connected. Today's MCPs use wire bonding, which not only can create a bandwidth bottleneck, but also use up substantial space by creating vertical gaps between dies. There are additional running down the edge of the dies, which results in a slight increase of the footprint of a single die.
A similar stacking approach was described by Intel at the Spring Developer Forum in March 2005, where Justin Rattner, then head of the corporate technology group and today chief technology officer, outlined the firm's ideas of using "through silicon via" interconnection technology to create "3D" packages.
