Intel will reveal specifics about its upcoming Xe graphics hardware architecture in an in-depth presentation at the annual Game Developers Conference (GDC) in March. Some of the “powerful” new features will include hardware-accelerated ray tracing (opens in new tab) and compute, geometry and throughput improvements.
GDC, described as the world's largest professional game industry event, is March 16 to 20 in San Francisco. On Tuesday, Antoine Cohade from Intel’s gaming developer relations announced on Twitter (opens in new tab) that he would give a presentation called A Primer on Intel Graphics Xe Architecture. The presentation isn't surprising, as last year Cohade also detailed Ice Lake’s Gen11 (opens in new tab) graphics architecture at GDC 2019.
“Intel's brand new Xe Architecture, has been teased for a while, and is scheduled for release later this year," the description of the presentation on the GDC session scheduler (opens in new tab) reads. "This update brings a significant compute, geometry and throughput improvements over today's widely used Gen9 and Gen11 graphics.”
The listing further notes that the architecture tour will detail the structure of the its building blocks and their performance implications. For software developers, it will also explain how to optimize for these features. The target audience are game and engine developers and engineers with an interest in hardware.
On Twitter (opens in new tab), Cohade also said that he would address questions of how Xe differs from previous generations and how it affects optimizations, differences between the discrete and integrated versions of Xe and ray tracing (opens in new tab) support.
Concerning the difference between the discrete and integrated version, Mike Burrows, CTO and Director of Advanced Technologies Group, Gaming & Graphics at Intel, earlier this month said on Twitter (opens in new tab) that the discrete variant has the benefit of dedicated memory, dedicated power and better thermals. He also said there is “lots of potential benefits” to having the same graphics architecture integrated on the same CPU side and also as a discrete variant. This could tantalizingly refer to the integrated and discrete graphics working together (opens in new tab).
Various pieces of information about Xe have indeed dripped into the public domain since Intel’s announcement of the graphics architecture in December 2018. This information includes:
- A GitHub patch note revealing (opens in new tab) that “Gen12 will be one of the biggest ISA updates in the history of the Gen architecture” and information about a display feature
- Intel’s announcement (opens in new tab) that it will be called DG1 and had successfully been powered on
- A possible June release date (opens in new tab)
- A listing (opens in new tab) that shows DG1 will have 96 EUs
- Intel’s DG1 development kit (opens in new tab) at CES (opens in new tab)in January
The company also disclosed in November some of the high-level features of the supercomputer-oriented flavor of the Xe architecture in the Ponte Vecchio (opens in new tab) 7nm GPU. Xe HPC features Xe Link, Xe Scalable Memory Fabric and a matrix engine with low-precision deep learning compute support.
The Xe architecture will have three microarchitecture instantiations called Xe LP, Xe HPC and Xe HP. Xe LP will be the mobile, sub-25W variant of Xe, which DG1 is based on; Ponte Vecchio will be based on Xe HPC and represent Intel's first 7nm product and Raja Koduri, SVP, chief architect and GM of architecture, graphics and software at Intel, described (opens in new tab) Xe HP as "the largest silicon designed in India and amongst the largest anywhere."