Intel CEO Brian Krzanich provided an update on its 3D XPoint efforts during the company's Q3 2016 earnings call and also noted that 3D XPoint would come to the second-generation Purley platform.
In the past, Krzanich has publicly outlined Intel's plan to leverage its 99.8% control of the data center CPU market as a beachhead to assault other segments; namely networking, memory, and storage. The company's revelations indicate that it is moving ahead with several initiatives that could bring key portions of these realms firmly under its control.
Intel's strategic machinations aren't secret, and three broad industry consortium's lined up this week to counter its moves. Let's dive in.
The Purley Connection
Purley is the next-generation server platform for Intel's Xeon processors based on the Skylake microarchitecture, which will supplant the current-gen Broadwell Xeon series. Intel's CEO noted that the company is already sampling Purley products to leading-edge customers and also provided more color on some of the planned features for the new series of Xeon processors;
"They’re seeing not only just an overall TCO performance advantage that we typically see with each one of these, but this also continues our integration of things like the omni-path fabric, [and] it has more integration of the silicon photonics, so it’s still the adjacency functions that are quite strong, and they will get more and better as we go through each one of these...there will be a second generation of Purley that includes 3D XPoint," said Krzanich. "It allows pooling of memory, and then there will be future ones that will allow additional pooling of things like FPGA. So, each one of these now add some additional features across the rack that really helps in the overall system performance." (via Seeking Alpha)
Intel has indicated in the past that it plans to bring 3D XPoint to market with its next-generation platforms. The news that 3D XPoint will not make its debut on the first-generation Purley products, which Intel still hasn't announced, might indicate that tighter integration will require more developmental efforts. Slotting 3D XPoint in as a storage device or DIMM is fairly straightforward, but bringing it on-package (or even on-die) presents daunting challenges.
As usual, several details have emerged on the Purley platform as it works its way to market. At Computex 2016, and we spotted the LGA 3647 socket that the new Purley processors will purportedly slot into. Intel employs the LGA 3647 socket for its Knights Landing (KNL) processors but has not officially verified that it uses it for the Purley platform. In either case, we weathered a barrage of takedown requests associated with our article, and more specifically, the pictures. Read into that as you will. Noctua also had a heatsink on display at Computex 2016 prominently labeled as compatible with the Intel Socket P (LGA 3647) for both Skylake-EP and Knights Landing, throwing another log on the speculatory fire.
The LGA 3647 socket certainly provides enough real estate to infuse plenty of high-powered additives, such as FPGA and GPU accelerators, but the Skylake-EP line may include on-package 3D XPoint, similar to the on-package MCDRAM (Multi-Channel DRAM) Micron HBM packages found on Knights Landing products (pictured). The Purley platform reportedly includes a new undefined UPI interconnect that supports 2- and 3-channel UPI options with 9.6 and 10.4 GT/s data transfers. UPI is widely thought to be a newer version of the venerable QPI interface. Intel has indicated that it plans to utilize proprietary interconnects for its 3D XPoint products, and the UPI interface tracks well with industry speculation that the new interconnect will feature a QPI-like interface.
All signs also point to an on-die Intel Omni-Path implementation (a 100Gbps fabric) with the Purley products, and Krzanich specifically called out the integration of Omni-Path and Intel's silicon photonics as key platform additives. Intel already has the support structure for on-die Omni-Path, such as the opening at the end of the LGA 3647 socket for KNL's networking adapter, so Purley’s Omni-Path integration plods through well-traveled territory.
Intel's $16.7 Altera acquisition laid the groundwork for Intel's plans to bring FPGAs on-die with CPUs; the company has even demoed working Xeon-FPGA hybrids at the 2016 OCP (Open Compute Project) Summit. Krzanich's comments indicate that it continues to be a strong part of Intel's strategy.
The data center is trending towards machine learning-fueled architectures, which isn't the best situation in terms of CPU sales. Machine learning workloads tend to execute on GPUs, FPGAs and ASICs, but also tend to require a CPU-driven platform. Merging CPUs and FPGAs into one package kills two birds with one stone; it reduces the need for a secondary FPGA (which will reduce power consumption and complexity) and also assures an automatic sale of the accompanying CPU.
Proprietary Interconnects Stir The Troubled Industry's Waters
Intel's intentions aren't exactly a secret, and its use of proprietary interconnects is raising the industry's ire.
If Intel puts 3D XPoint behind its own interconnects, particularly for on-package Xeon implementations and DIMMs, then it has a pretty solid start to controlling portions of the memory market. The company also has a strong presence in the storage world with its 3D NAND, and its return to manufacturing memory products (after a 31-year hiatus) at the Dalian fab indicates its continued commitment to that segment. Finally, Omni-Path, which Intel is pairing with its own silicon photonics products, puts the networking segment in a proprietary stranglehold.
Bringing all these technologies on-die, or even on-package, with its Xeon CPUs is the coup de grace that provides a chokehold on all three segments. On the one hand, it provides one central and optimized solution. On the other hand, it places yet more control in Intel's hands, which is somewhat scary considering the company already essentially owns the world's data centers. In the grand scheme of things, proprietary implementations aren't good for pricing nor innovation.
However, the industry isn't blind to these developments (or Intel's public statements). In fact, we have witnessed a massive reaction over the last few weeks as three new industry groups emerged with open interfaces to counter Intel's plans in the storage, memory, and networking areas. The Gen-Z consortium, OpenCAPI Consortium, and CCIX consortium are composed of broad groups, which include industry heavyweights such as AMD, Dell, EMC, Google, Mellanox, Micron, ARM, Broadcom, IBM, Seagate, Samsung, and Xilinx, and are working to create open alternatives to promote innovation and lower price structures.
The current state of application scaling, which is largely memory- and storage-bound, limits the gains from adding more compute to existing implementations. The new interconnects also aim to solve computing challenges without adding more cores, so it's easy to see how that could run counter to Intel's objectives.
Intel and Cisco are the most notable holdouts from all three of these new industry groups, but the message is clear; the industry wants, and needs, open interfaces. At this point, the only question is how Intel responds.
