Intel's Xeon E5-2600 v4 finds the company at the intersection of a waning desktop market and the exploding data center segment. Less momentum on the desktop side is naturally worrying; but being a leader in the high-growth enterprise space is a great place to be; Intel just happens to sell 99 percent of the world's processors destined for the data center. There is no single contender that poses an immediate threat to the company's dominance, though IBM's Power architecture and a budding Qualcomm initiative in China may gain ground over the long term.
The latest evolution in Intel's Xeon line-up is made possible by the Broadwell-EP architecture, manufactured on a 14nm process. That's a shrink of Haswell-EP's 22nm lithography. Many see Broadwell-EP as Intel's last attempt at satisfying the famed tick/tock cadence.
No doubt, Moore's Law is slowing to a crawl. The first precursors became evident in July of last year when the company indicated it'd push back its 10nm process to 2017. A recent 10-K filing merely formalized the obvious and inevitable.
Intel's filing indicates that it is migrating from the familiar tick/tock tempo to a slower process, architecture and optimization cadence. It appears that the challenges of shrinking transistors are becoming too difficult, and too expensive, to circumvent at such a rapid pace.
The new rhythm will lengthen the amount of time the company utilizes its 14nm and 10nm processes, which makes good business sense. Financially, it is better for Intel to recoup more of its investment into increasingly expensive tooling while extending its profitability window for each processor generation. There is no clear threat to the company's dominance, so its technological leadership position isn't at risk.
The Xeon E5-2600 v4 family wades into this new reality with a number of improvements that extend beyond more cores and cache (though it includes those as well). Perhaps that'll gives us some insight into Intel's plans moving forward.
Intel Xeon E5-2600 v4 Series
The Broadwell-EP microarchitecture increases the maximum number of cores/threads from 18/36 to 22/44, and also makes room for up to 55MB of shared L3 cache (up from 45MB). Intel still enables four channels of DDR4 memory, but increases the peak data rate to 2400 MT/s (a 15 percent improvement). Intel also added new memory features, such as support for 3DS LRDIMMs and DDR4 Write CRC (an enhanced form of error control).
We're told the CPUs benefit from an IPC increase of 5.5 percent or so through a series of optimizations we'll cover on the following page, and are socket-compatible replacements for Xeon E5-2600 v3-based Grantley systems (LGA2011-3). Existing motherboards/servers will require a BIOS update, though. The existing C610 series chipset soldiers on, meaning that most platform features remain unchanged. You still get 40 lanes of PCIe 3.0 and two QPI 1.1 ports, for example.
The E5-2600 v4s offer a different base frequency and Turbo Boost setting for AVX and non-AVX functions, but Intel notably allows each core to operate in either mode without affecting the clock rate of other cores. In the past, every core ran at a lower base and peak Turbo Boost frequency if the cores were running a mix of AVX and non-AVX code. That restriction is no longer in place.
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Our Xeon E5-2697 v4 sample features 18 Hyper-Threaded cores and provides a non-AVX base frequency of 2.3GHz, peaking at 3.6GHz under Turbo Boost. Running AVX code, the base drops to 2GHz, while Turbo can still take you to 3.6GHz.
The Product Stack
The fourth-generation E5-2600 series features 22 models designed for a wide range of workloads. Intel groups the processors into High Core Count (HCC), Medium Core Count (MCC) and Low Core Count (LCC) segments ranging from four cores and 10MB of LLC to 22 cores with 55MB of cache.
New Intel 3D NAND SSDs
All of the processing power in the world is worthless if your CPU is waiting on the storage subsystem. Intel helped foment the SSD revolution when it introduced its first datacenter-oriented drives. Of course, the move was a strategic one. Intel makes more money selling storage. In turn, SSDs help unlock the potential of multi-core processors, encouraging more Xeon business.
Intel and Micron produce NAND in the jointly operated venture called IMFT, which recently announced 3D NAND-based products. Intel chose to launch two drives based on the technology, its DC P3520 and DC P3320 SSDs, in tandem with Broadwell-EP.
The DC P3320 series is news to us, but the DC P3520 is not. We discovered a document back in August that foretold the release of Intel's DC P3608, and it also included pertinent information on the DC P3520. Intel briefed us on the DC P3320 during its Broadwell disclosure. However, it kept information about the DC P3520 to itself. Don't worry, though. We have the scoop on all of Intel's new SSDs, including dual-port NVMe-based offerings, on page three.
First, let's take a closer look at the Broadwell-EP microarchitecture.
In most server applications it doesn't matter as much as multithreaded performance. If you need single-core strength, getting a consumer chip is actually better, but you probably aren't running a server if single-threaded is your focus.
And the fact that Intel even released low-core high-clock SKUs is an acknowledgement of this continuing need. Clock just not as high as I'd read. With the other specs basically matching the Haswell version, the only difference is ~5% IPC improvement. Seems pretty poor improvement, for a die-shrink.
Model: Intel Xeon E5-2602 V4
Base clock: 5.1 GHz
Turbo clock: TBD
L3 Cache: 5 MB
Given what we know about 2.5 MB/core of L3 Cache, the 5 MB figure sounds suspicious. It's conceivable they could disable some to hit the target TDP, I guess.
I'm not saying the 5Ghz rumor is true but Intel has always known which chips can hit higher clocks during certification if the chip is a top end or low end chip cores disabled etc. I'm sure they could cherry pick a few to sell for $$$ if they wanted. Now are they I have no real idea.
There are obviously things you can do in chip design that allow one to reach different timing targets. And I was hoping they might've refined their 14 nm process, since the time the first Broadwells launched. So, I thought, with more TDP headroom afforded by this socket (roughly double what Skylake has to work with), maybe they could do it.
I thought maybe Intel was addressing some pent-up demand for high clockspeed applications. That said, it seemed particularly odd in Broadwell, given that it generally seems oriented towards lower clockspeed / lower power applications.
But maybe it was a typo, or even a blatant lie, in order to track down leakers.