Intel Xeon E5-2600 v4 Broadwell-EP Review
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Page 1:Introduction
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Page 2:Broadwell-EP Architecture
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Page 3:Intel Test Platforms And How We Test
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Page 4:Supermicro And NVMe RAID Testing: 3 Million IOPS And 21 GB/s
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Page 5:Intel's 3D NAND SSD Debut: DC P3520/P3320 And DC3700/3600
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Page 6:Benchmarks
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Page 7:Additional Benchmarks
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Page 8:Power Consumption
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Page 9:Conclusion
Conclusion
Intel's switch to the process, architecture and optimization cadence is a clear indicator that the heady days of Moore's Law is drawing to a close. Over the last few decades, Intel picked the low-hanging fruit from the transistor tree as it moved forward at an incredible pace, but now we're finding each processor generation offering smaller and smaller performance improvements.
The majority of datacenter and enterprise customers are locked into three- or five-year refresh cycles due to maintenance contracts, and as those contracts expire, they upgrade to the newest platforms. This means that the majority of Broadwell-EP customers will be migrating from either Sandy Bridge or Ivy Bridge, and not replacing Haswell-EP-based processors with newer Broadwell-EP models.
As a result, they'll reap the benefits of not only Intel's Broadwell-EP design, but also the mature C610-series chipsets, which continue to find use with the fourth-generation Xeon E5s (updated with fresh firmware, of course). That platform controller hub family merely serves to support a well-endowed host processor. The PCH has limited PCIe 2.0, some built-in USB 3.0 and quite a bit of SATA connectivity. Really, it's the Xeon's big PCIe 3.0 controller, fast QPI links and DDR4 memory controllers (now able to accommodate 2400 MT/s modules) that do the heavy lifting.
The CPU's key advances include a top-end model with four more physical cores, a roughly 5.5 percent improvement in IPC throughput and a last-level cache increase from 45 to 55MB. Our benchmarks show the Xeon E5-2600 v4 serving up nice performance increases through most of the suite. Numerous platform-level improvements offer massive performance advantages to anyone migrating from old Sandy Bridge and Ivy Bridge servers. On the flip side, there's probably not enough reason for most businesses to ditch Haswell-EP in favor of Broadwell-EP, unless they really need a specific new feature.
Speaking of new features, they appear to be an increasing focus at Intel as the glory days of massive performance gains fade into history. In lieu of big speed-ups, Broadwell-EP includes some extras designed to enhance performance and usability in a variety of applications. VM-centric optimizations should enjoy considerable use in the wild, and the new orchestration tools allow administrators to monitor, manage and optimize with a heretofore-unseen level of granularity. Increased performance and manageability in security-related tasks through faster encryption/decryption, a new random seed generator, SMNAP and Crypto Speedup will come in handy as well.
Intel is wisely using its Broadwell-EP launch as a springboard to introduce a number of high-powered SSDs, too. The meteoric rise of solid-state storage in the datacenter is making it easier to fully utilize potent multi-core CPUs, and matching speedy NVMe-based drives up to the latest in processor technology proves key in bleeding-edge applications, as evidenced by our NVMe RAID tests.
Many enthusiasts are looking to Skylake as the next truly revolutionary advance in processor technology, and there are predictions that it will support 3D XPoint additives and on-die Omni-Path adapters. Sure, Skylake is exciting. But the 14nm node might have more to offer in the near term as well.
Intel recently displayed Arria 10 FPGAs and what appeared to be a Broadwell die on the same package at the Open Compute Summit. It announced that products with this design will ship in 2016. The company's recent Altera purchase looks like it's bearing fruit already, and we may see an interesting marriage of CPU and FPGA on the same die during the transition to process, architecture and optimization.
In the meantime, Intel's Xeon E5-2600 v4 family provides an attractive upgrade path that offers gains in performance, cores, cache and power consumption that will satisfy the vast majority of users, and in particular, those migrating from Ivy and Sandy Bridge.
The E5-2600 v4 family and the Broadwell-EP microarchitecture represent the latest Xeon generational advance, bringing the welcome addition of more cores, cache and IPC performance along with a suite of new management and optimization features.
Intel Xeon E5-2600 v4
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Paul Alcorn is a Contributing Editor for Tom's IT Pro and Tom's Hardware, covering Storage. Follow him on Twitter and on Google+. Follow us on Facebook, Google+, RSS, Twitter and YouTube.
In most server applications it doesn't matter as much as multithreaded performance. If you need single-core strength, getting a consumer chip is actually better, but you probably aren't running a server if single-threaded is your focus.
I read the rumors on that as well, but nothing official has surfaced as of yet to my knowledge.
And the fact that Intel even released low-core high-clock SKUs is an acknowledgement of this continuing need. Clock just not as high as I'd read. With the other specs basically matching the Haswell version, the only difference is ~5% IPC improvement. Seems pretty poor improvement, for a die-shrink.
On wccftech (not the most reliable source, I know), they claimed:
Model: Intel Xeon E5-2602 V4
Cores/threads: 4/8
Base clock: 5.1 GHz
Turbo clock: TBD
L3 Cache: 5 MB
TDP: 165W
Given what we know about 2.5 MB/core of L3 Cache, the 5 MB figure sounds suspicious. It's conceivable they could disable some to hit the target TDP, I guess.
I'm not saying the 5Ghz rumor is true but Intel has always known which chips can hit higher clocks during certification if the chip is a top end or low end chip cores disabled etc. I'm sure they could cherry pick a few to sell for $$$ if they wanted. Now are they I have no real idea.
There are obviously things you can do in chip design that allow one to reach different timing targets. And I was hoping they might've refined their 14 nm process, since the time the first Broadwells launched. So, I thought, with more TDP headroom afforded by this socket (roughly double what Skylake has to work with), maybe they could do it.
I thought maybe Intel was addressing some pent-up demand for high clockspeed applications. That said, it seemed particularly odd in Broadwell, given that it generally seems oriented towards lower clockspeed / lower power applications.
But maybe it was a typo, or even a blatant lie, in order to track down leakers.
proper binning and sold specifically as that because of what it hits, this could double/triple the value of the chip at least compared to other lower binned versions.
A really high clock on a server platform seems like an overclocker's dream to me. Stability and performance. Not to mention that server processors use solder instead of that cheap paste Intel uses in their consumer processors.
The article does not state that it is more than the *combined* total of 182 countries, merely that it consumes more power than each of them compared individually. You are right,mentioning that it would place 11th in the world is probably a better way of stating the statistic.
I remember reading that the Pentium 4 was originally designed to scale up to 10 GHz, by the end of its production. Of course, back then, the only way they could hit those speeds was to use really long pipelines composed of very simple stages. Then, when they discovered that leakage of newer process nodes was higher than anticipated, they were left with a very inefficient architecture that was stuck below the clock speeds that would've made it competitive.
These days, I think Intel could do it without such a drastic architectural tradeoff. But it still comes down to a power vs. clock, no matter what.
Those IBM chips had a really long pipeline to allow clock speeds that high as well as an SOI process node basically built from the ground up for them. I wonder what version of 14nm Intel is using for Broadwell-E/EP/EX as I know they had one version they used for the Broadwell-U,Y,H,DT(C) and when they moved to Skylake they used an updated version of 14nm. Is it possible that Broadwell_E/EP/EX are using the updated 14nm process?