Memory Bandwidth And Requirements For Dual Channel
With optimal features, the theoretical memory bandwidth is 6.4 GB/s, which is therefore synchronous to the bandwidth of the CPU. If desired, however, asynchronous operation is also possible. The 6.4 GB/s value is calculated from 200 MHz memory clock x 8 bit x 2 (Double Data Rate) x 2 channels.
In order to activate dual-channel mode, the DIMM configuration for each channel must be consistent with that of the other, including:
- the same module capacity in pairs (2 x 128 MByte, 2 x 256 MByte, 2 x 512 MByte, etc.);
- the same DRAM technology (2 x 256 Mbit or 2 x 512 Mbit);
- the same DRAM bus width (x8 or x16);
- single-sided or dual-sided modules must be used in pairs;
- memory slots must be fitted symmetrically (first Channel A, Slot 0 and Channel B, Slot 0, then Channel A, Slot 1 and Channel B, Slot 1).
Furthermore, the 875 chipset supports ECC memory. Dual-channel operation could work if modules from different manufacturers are used. If the timing specifications (CL2 with CL3) or the DDR speed (DDR400 with DDR333) are different, then the chipset uses the slowest component in the chain.
Four-Layer Design, Despite Dual Channel? It Works!
Motherboards with six layers became the fashion when dual-channel solutions were introduced. Today, manufacturers use this method to produce platforms with SiS655, Nvidia nForce2, or even Intel E7205/ Granite Bay. Thus, the 875P Northbridge was constructed in such a way that one memory channel could be connected to one layer and the second channel to another layer. To be exact, channel A is connected to the top layer, and channel B with the bottom layer.
Intel's reference design: despite dual memory, the inexpensive four-layer technique is possible because the chipset sits at a 45 degree angle on the board. Memory channel A is connected to the top layer, channel B with the bottom layer.
One DDR channel needs 64 data lines and 13 address lines. The 875 actually uses 119 lines per channel (including GNDs), 9 are reserved for ECC.