AgileX In-Depth: PCIe Gen 5, DDR5, HBM3 and Optane DIMM Support

OneAPI and the AgileX Family

Enabling Any Developer Through OneAPI

To make FPGAs broadly accessible to traditional software developers, AgileX will support the OneAPI programming environment. While there is a lot of hardware in AgileX, Intel argues that its (OneAPI) software is more important than the hardware for AgileX. Intel says the hardware really doesn't matter if they can't make it easier to program FPGAs, which in turn expands the user base. For their core RTL developers, Intel claims a 30% reduction in compile times and a 15% improvement in memory utilization with the latest version of Quartus Prime. This version is coming this month and will also add support for AgileX.

The Product Family

Intel announced three series as part of the AgileX product family.

The F-series is the most basic, and we think it is probably the only one that will be available initially. It supports up to 58G transceivers, PCIe Gen4 and DDR4. The base die also contains a quadcore A53 CPU, although Intel has strongly hinted that there will a chiplet with an A7x series octa-core SoC.

The point of the A53 is not to burden the base FPGA with too many CPU transistors, with the general message being that higher performance CPUs and higher core counts chiplets can be provided in extra tiles via EMIB, so only those customers who need it have to pay for it.

The I-series is meant for bandwidth-intensive applications, so it includes 112G transceivers and PCIe Gen5 support. This allows the coherent memory attachment to Xeon Scalable to be added, as the CXL interconnect requires PCIe 5.0. Lastly, the M-series adds high-bandwidth memory (HBM).

The first device becomes available in Q3, which Intel said is “right on schedule with what we expected.” We're sure this is a statement about product sampling because Intel gave a presentation in late 2017 that mentioned the second half of 2018 for sampling. General availability typically begins about a year after sampling.

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