TSMC says it doesn't need High-NA EUV chipmaking tools for 1.6nm-class node, but Intel has championed the tech

ASML
(Image credit: ASML)

TSMC says its newest process tech doesn't need ASML's High-NA EUV chipmaking tools that have been championed by Intel, but the foundry is exploring the tech for future use.

According to Reuters, Zhang told attendees of the event that the A16 process technology will not need the next-generation EUV lithography tools. This implies means that TSMC has found ways to cost-efficiently use EUV double patterning and pattern shaping to increase the achievable critical dimension of a modern Low-NA litho system beyond 13nm. In contrast, Intel plans to insert High-NA EUV tools with its 14A manufacturing technology after it learns how to efficiently use them with its 18A production node.

TSMC is not standing still, though. The company is exploring High-NA EUV lithography for its future process technologies. The A14 node will follow A16, and as TSMC noted in its 2023 Annual Report, A14 development is well underway. 

"TSMC started development and made good progress on 14 Angstrom (A14) technology, which aims to further improve speed, power, density and cost," the company's Annual Report reads. "Looking ahead to A14 and beyond, TSMC R&D will continue to explore next generation EUV (extreme ultraviolet) lithography scanners, conduct research on mask pellicles and blanks to support leading-edge technology and extend Moore's Law."

Using High-NA EUV lithography systems greatly increases fab costs as each tool costs $385 million or more depending on the configuration. Chipmakers tend to re-use as many tools as possible, so TSMC may not be inclined to use High-NA EUV before it runs out of ways to introduce improvements to its production capabilities using Low-NA EUV tools. For example, last year, the company improved the critical dimension and pattern fidelity as well as lowered defect density by modifying photoresist and blank materials as well as optimizing mask process recipes. It also uses deep learning for inspection and discovering defects.

"In 2023, to achieve the wafer yield and productivity for lithography requirements at 2nm node, the R&D team improved the critical dimension, pattern fidelity, overlay stability, exposure durability, and defect mitigation of curvilinear patterns by EUV photoresist and blank material modification, multi-beam writer resolution enhancement, mask process recipe optimization, and advanced deep learning inspection," TSMC said in the report. "Future improvements will focus on developing new blank materials and new mask process technology at the A14 node and beyond."

TSMC's announcement of its A16 process technology (1.6nm-class) with Super Power Rail backside power delivery came as a surprise at the company's North America Technology Symposium 2024. Kevin Zhang, Vice President of Business Development at TSMC, said that the world's largest contract chipmaker had to speed up development of the production node due to rising demand from the AI sector, reports Reuters.

Anton Shilov
Freelance News Writer

Anton Shilov is a Freelance News Writer at Tom’s Hardware US. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

  • thestryker
    This is basically the best opportunity Intel has to regain market leadership on process node. BSP was originally supposed to land with N2, but is now A16 which means TSMC should be competing with Intel's refined 18A nodes and 14A. We need there to be volume competition on the leading edge nodes so some of those margins can be cut (not that I think the savings will make their way to consumers, but maybe prevent/slow additional price hikes).
    Reply
  • Lucky_SLS
    I think in a few years time, the industry might focus more on silicon alternatives for higher performance.
    Reply
  • eX_Arkangel
    thestryker said:
    This is basically the best opportunity Intel has to regain market leadership on process node. BSP was originally supposed to land with N2, but is now A16 which means TSMC should be competing with Intel's refined 18A nodes and 14A. We need there to be volume competition on the leading edge nodes so some of those margins can be cut (not that I think the savings will make their way to consumers, but maybe prevent/slow additional price hikes).
    i dont think so, Hight-NA is just an optical (lens) optimization for EUV, but not even close as a game changer as DUV to EUV, also there are other reasons why Intel is rushing to High-NA, the main being their very low count of current EUV machines unlike TSMC which has the biggest amount by far, Intel discarded EUV and tried to force DUV to its very limits and failed, i dont think TSMC will make the same mistake, but High-NA is not the same nor will bring massive tech improvements, its a no brainer for Intel, as they have to build up their EUV lines no matter what, so they take the latest EUV machine.
    Reply
  • eX_Arkangel
    Lucky_SLS said:
    I think in a few years time, the industry might focus more on silicon alternatives for higher performance.
    we are getting to the physics wall with current methods.. the next big things are packaging and interconnects/stitching methods of several dies to be seen as one (NV B200). Until a new groundbreaking method/materials are discovered and then onto the PicoM race we go.
    Reply
  • dalek1234
    eX_Arkangel said:
    i dont think so, Hight-NA is just an optical (lens) optimization for EUV, ....
    That was informative. Thanks
    Reply
  • thestryker
    eX_Arkangel said:
    i dont think so, Hight-NA is just an optical (lens) optimization for EUV, but not even close as a game changer as DUV to EUV, also there are other reasons why Intel is rushing to High-NA, the main being their very low count of current EUV machines unlike TSMC which has the biggest amount by far, Intel discarded EUV and tried to force DUV to its very limits and failed, i dont think TSMC will make the same mistake, but High-NA is not the same nor will bring massive tech improvements, its a no brainer for Intel, as they have to build up their EUV lines no matter what, so they take the latest EUV machine.
    I'm not sure why you quoted me and went on a rambling statement about High-NA. I didn't talk about High-NA at all and wasn't even remotely referring to it. Intel is bringing GAA and BSPDN to their nodes before TSMC which gives them an advantage on implementation and in turn an opportunity to get ahead in process node.

    The advantage High-NA brings is more of a long term situation than anything else. Given the very low volume of machines being manufactured it makes sense TSMC is waiting. Only time will tell whether or not that was the correct gamble to take.
    Reply
  • eX_Arkangel
    thestryker said:
    I'm not sure why you quoted me and went on a rambling statement about High-NA. I didn't talk about High-NA at all and wasn't even remotely referring to it. Intel is bringing GAA and BSPDN to their nodes before TSMC which gives them an advantage on implementation and in turn an opportunity to get ahead in process node.

    The advantage High-NA brings is more of a long term situation than anything else. Given the very low volume of machines being manufactured it makes sense TSMC is waiting. Only time will tell whether or not that was the correct gamble to take.
    maybe because the OG Article is about TSMC not rushing to Hi-NA?, hence the "rambling" about it, also that in the article and your post both "expect" same opportunities from this for Intel, so, i just gave my "personal" opinion on the matter using yours as a debatable point.
    If based on transistor tech only then maybe Intel can tie to TSMC again, but with how IFS has been going lately its very doubtful, 5 nodes in 2 years ended being 2 nodes in 5 years IRL, so theres no real fact to back Intel claims of delivering on their roadmaps or their tech anymore (at least for mass production usage).
    Also TSMC has always took things slow and steady.
    Reply
  • thestryker
    eX_Arkangel said:
    maybe because the OG Article is about TSMC not rushing to Hi-NA?, hence the "rambling" about it, also that in the article and your post both "expect" same opportunities from this for Intel, so, i just gave my "personal" opinion on the matter using yours as a debatable point.
    Ah so you just misunderstood what I was talking about entirely because of the article. I was referring to the process node technology delays not High-NA specifically. High-NA doesn't enable those technologies for Intel as they're not utilizing it for a production node until 14A. TSMC will be competing with mature BSPDN and High-NA with their A16 node because they delayed their BSPDN. It's an important distinction.
    eX_Arkangel said:
    If based on transistor tech only then maybe Intel can tie to TSMC again, but with how IFS has been going lately its very doubtful, 5 nodes in 2 years ended being 2 nodes in 5 years IRL, so theres no real fact to back Intel claims of delivering on their roadmaps or their tech anymore (at least for mass production usage).
    It's a 5 nodes in 4 years plan and their counting started with Intel 7 in 2021. They're currently shipping 2 with the third in mass production so we'll see if that slips or not though. They claimed earlier this year it was still on track which would mean 18A in mass production next year.
    Reply