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Xeon Phi: Intel's Larrabee-Derived Card In TACC's Supercomputer

Introducing Intel Xeon Phi

Intel has its sights on supercomputers capable of exaFLOP-class performance by 2020. To put that in perspective, we were looking at teraFLOPS-capable systems in the mid-1990s. And today's fastest supercomputers are in the tens of petaFLOPS. Achieving one exaFLOPS requires a 1000x speed-up compared to a one-petaFLOPS machine. That's a stunningly-large number.

Getting there is unquestionably going to require accelerators, as Intel calls them. AMD and Nvidia are content to credit their GPUs for the sudden surge in floating-point performance wielded by today's fastest supercomputers. But all parties will agree that the future of this space doesn't belong exclusively to Xeons or Opterons. Most analysts instead expect a mix of compute resources from those big CPUs to smaller, more specialized cores.

Today, in an effort to face the head start both GPU vendors already have in this space, and to address the surging demand for compute performance, Intel is introducing its Xeon Phi Coprocessor 5110P and announcing the Xeon Phi Coprocessor 3100-series, which will be released in 2013.

In essence, Xeon Phi takes 60 (at least in the announced 5110P SKU) x86 cores with big 512-bit vector units, runs them in excess of 1 GHz, and yields more than 1 teraFLOPS of double-precision performance on a dual-slot PCI Express card with a custom Linux distribution. That same Xeon Phi 5110P includes 8 GB of GDDR5 memory, although Intel plans to arm the 3100-series cards with 6 GB. To be sure, the cores are not designed to address the general-purpose workloads you'd tackle with a third-gen Core or even Atom processor. Rather, they excel in parallelized tasks able to leverage those many cores to greater effect. 

Why might you need an accelerator card like the Phi? Weather modeling, medical imaging, energy exploration, simulation, financial analysis, content creation, and manufacturing are all fields currently leveraging hardware from AMD and Nvidia for their compute power. Intel is simply trying to do the same thing with a product that doesn't require coding in CUDA or OpenCL. Instead, ISVs can optimize for Phi using C, C++, and Fortran, with specific additions to the code that accommodate and utilize the accelerator.

Of course, getting here was no easy task, and many enthusiasts will recognize the Larrabee business unit name, which came to be as far back as 2005. In '04, Intel embarked on a multi-year project after seeing that clock rates could not scale indefinitely due to material (process) and power constraints. Larrabee was years in the making, feeding us a stream of both promising and embarrassing headlines over the course of its development.

The milestones on Intel's timeline were all met with great interest as the company evangelized a concept of many integrated cores that was different from what its competition was doing. Of course, when it came to be known that Larrabee would under-perform existing graphics processors from AMD and Nvidia, Intel canceled its plan to introduce a graphics card of its own and instead focused on the architecture's high-performance computing capabilities. As we'll see, pre-production examples of the hardware are already part of the Top500 project. 

As part of its Xeon Phi launch, Intel flew members of the press into the Texas Advanced Computing Center to see the Stampede supercomputer, which employs Xeon Phi. Of course, we were able to sneak in a few photos of one of the world's fastest computing systems during the trip. But before we're able to understand Intel's approach to HPC, we need to understand Larrabee. So, let's take a brief step back in time.