Hidden inside the Raspberry Pi 4 is a PCI Express interface, and hackers are making the most of it.
The PCI-SIG organization on Wednesday released the final PCI Express 5.0 specification. The new interconnect standard doubles the bandwidth to 32GT/s per lane, less than two years after PCIe 4.0.
Last week at NVIDIA's GPU Technology Conference (GTC), One Stop Systems introduced the industry's first PCIe 4.0 backplane.
E1000 takes shape at VM World delivering 1M IOPS with host power fail protection and a low cost design.
This week we got the first details about the fourth generation of the PCI express spec. PCIe 4.0 will have a base speed of 16 Gbps per data link.
The PCI-SIG has launched M-PCIe for mobile devices, and introduced several other specs including M.2, a natural transition from the Mini Card and Half Mini Card.
New specification allows PCIe protocols to operate over MIPI M-PHY to deliver a low-power, high-performance I/O solution.