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AMD Explains Advantages of High Density (Thin) Libraries

By - Source: Tom's Hardware US | B 13 comments

At today's Hot Chips Symposium, Mark Papermaster, Senior Vice President and CTO at AMD, talks about the upcoming "High Density (Thin) Libraries"

We have seen the improvements that the "Steamroller" will offer in performance per watt with its design improvements. In addition to those improvements, AMD will be using "dense" or "thin" libraries employed by its GPU design teams, but for CPU implementation.

AMD told us that products currently shipping with 32nm use a combination of automated place and route and hand-placed semi-custom design (top plot), which reduces power and area somewhat. To deliver more power efficient computations, AMD has employed a high-density cell library to reduce the area and power by 30 percent (bottom plot). The design yields a more portable and energy efficiency CPU core employing industry standard design methodologies well adapted to a foundry model. These improvements, according to AMD, are yielding a 15 to 30 percent lower energy per operation for power constrained designs, as compared to a full process node improvement.

Look for more details from AMD during Hot Chips Symposium on its Surround Computing and Steamroller.

 

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  • 1 Hide
    wiyosaya , August 28, 2012 9:24 PM
    In some respects, this sounds like the programmable gate array concept. It is interesting to see this adapted to non-programmable chip design.

    I am somewhat surprised, though, that this implies that such optimization was never before computerized. I would be really surprised if there were no computer optimization of chip layouts before this.

    So, is this just AMDs marketing engine at the helm again?
  • 6 Hide
    madooo12 , August 28, 2012 9:30 PM
    read on anandtech that they will only be used in excavator
  • 0 Hide
    Ragnar-Kon , August 28, 2012 9:31 PM
    So more logic in a smaller area. Basically what chip designers have been doing since ICs were first invented. Nothing new...

    EDIT: My bad, more logic in a smaller area without a die shrink. So essentially just housecleaning on current libraries. Still clever marketing.
    It is a die shrink, myyyy baaddddd. Doesn't seem anything like the 3-D transistors used in Intel's 22nm process though. Not that is necessarily a bad thing, I just thought it was similar to that originally.
  • 6 Hide
    ikefu , August 28, 2012 9:47 PM
    Its also lower power consumption without a die shrink, which means more thermal headroom to up frequencies, add a die shrink on top of this and you suddenly gets LOTS more headroom.

    So no, not just good marketing. But I am confused why this didn't happen already.

    Doesn't fix their instruction per clock efficiency problem, but it will help increase CPU frequencies to cover for it while they work on that problem.
  • 1 Hide
    Shin-san , August 29, 2012 12:09 AM
    Okay, what about the performance?!
    ikefuIts also lower power consumption without a die shrink, which means more thermal headroom to up frequencies, add a die shrink on top of this and you suddenly gets LOTS more headroom.So no, not just good marketing. But I am confused why this didn't happen already.Doesn't fix their instruction per clock efficiency problem, but it will help increase CPU frequencies to cover for it while they work on that problem.

    I'm thinking that they are going for raw clocks.
  • 1 Hide
    acadia11 , August 29, 2012 2:14 AM
    What you talking bout Willis?
  • 1 Hide
    acadia11 , August 29, 2012 2:17 AM
    Ragnar-KonSo more logic in a smaller area. Basically what chip designers have been doing since ICs were first invented. Nothing new... move along.But yeah... marketing at its finest (or worst?).EDIT: My bad, more logic in a smaller area without a die shrink. So essentially just housecleaning on current libraries. Still clever marketing.


    I thought it was going to be used in asphalt paver?

    Ok , I just made that name up there is no chip asphalt paver.
  • 2 Hide
    blazorthon , August 29, 2012 2:51 AM
    This could be used in place of a die shrink or at least with a minor die shrink rather than a major die shrink. That's quite something even if it won't be used until Excavator.
  • -1 Hide
    pharoahhalfdead , August 29, 2012 4:01 AM
    "Our next gen cpu's will feature..." coming soon... at the end of 2013.
  • -3 Hide
    dusk007 , August 29, 2012 9:14 AM
    I don't get that AMD focus on raw high clocks anyway.
    Todays CPUs are constrained by heat and power anyway before the maximum clock is hit.
    That is like building an aircraft turbine that can work well at Mach 2 while the entire airframe and efficiency requirements and noise regulations won't let the plane past 950 km/h anyway.
  • 1 Hide
    cjl , August 29, 2012 9:48 AM
    Actually, if you believe Anandtech at least, this change reduces the maximum frequency that the circuit is capable of running, but it improves power consumption and die size. So, if anything, this is a transition away from the maximum frequency approach, and towards a more power-efficient design.
  • -1 Hide
    ashinms , August 29, 2012 12:11 PM
    So this is AMD's response to FINFETs....
  • 1 Hide
    fazers_on_stun , August 29, 2012 1:42 PM
    Seems like the new layout with the dense libraries reduces superfluous transistor counts, so that would reduce the power consumption and reduce the die size. So yeah I imagine higher clocks at the same TDP as BD, or lower TDP at the same clocks. IIRC BD originally was stated (by AMD's idiot marketing dept :p ) to have 2 BN transistors, and then a couple months later that was reduced to 1.4BN when the actual engineers who designed it corrected the marketing dept's misstatement.

    Anyway, I wonder if this is still 32nm - article didn't mention that. If Steamroller (due out in 2H2013?) or even later with Excavator (2014?), then it seems GF is not making progress with 22nm as quickly as they said previously..