Intel Demos Meteor Lake CPU with On-Package LPDDR5X

Meteor Lake
(Image credit: Intel)

Intel on Wednesday demonstrated advancements of its sophisticated packaging technologies such as EMIB (embedded multi-die interconnect bridge) and Foveros and showed off its upcoming Meteor Lake processor with on-package LPDDR5X memory. It looks like Intel has taken a page from Apple's book as the company has been installing LPDDR memory on its M1 and M2 packages for a while now. 

The product demonstrated by Intel is its quad-tile Meteor Lake CPU, which uses Foveros packaging for its chiplets and carries 16GB of Samsung's LPDDR5X-7500 memory. Actual configuration of the CPU is unknown, but 16GB of memory can provide a peak bandwidth of 120 GB/s, which is considerably higher than the peak bandwidth provided by a memory subsystem featuring DDR5-5200 or LPDDR5-6400.

Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

  • ezst036
    Admin said:
    It looks like Intel has taken a page from Apple's book as the company has been installing LPDDR memory on its M1 and M2 packages for a while now.

    The product demonstrated by Intel is its quad-tile Meteor Lake CPU, which uses Foveros packaging for its chiplets and carries 16GB of Samsung's LPDDR5X-7500 memory. Actual configuration of the CPU is unknown, but 16GB of memory can provide a peak bandwidth of 120 GB/s

    Looks like this sits firmly inbetween M1 and M1 Pro.

    https://www.tomshardware.com/news/apple-m1-pro-max-everything-we-know
    68.25 GBps200 GBps
    Just a little bit above M2, which is 100Gbps. And what level is this anyways, like a level 9 cache?
    Reply
  • JamesJones44
    If the performance and battery life are there I think OEMs like Dell and HP will bite all day long. Your lower end is doubtful, but we will see.
    Reply
  • rluker5
    I like the on package memory. Even if it only helps performance and efficiency a bit that is better than nothing.

    But where is this interposer with the cache that was rumored. I had my hopes up.

    Also Apple was first with the on package dram, but that was with Crystalwell, an Intel product back in 2014.
    Reply
  • JamesJones44
    The big question I have is does the iGPU have access to this memory in the same way Apple Silicon does? If it does there could be a nice boost for the iGPU in these processors. If not, it may not be as dramatic of a bump that Apple Silicon gets from it's Unified Memory structure.
    Reply
  • jkflipflop98
    rluker5 said:
    I like the on package memory. Even if it only helps performance and efficiency a bit that is better than nothing.

    But where is this interposer with the cache that was rumored. I had my hopes up.

    Also Apple was first with the on package dram, but that was with Crystalwell, an Intel product back in 2014.

    Wut? Exactly what advantages do you suppose putting cache on the interposer will provide? How would you even use that? The interposer is a fancy smart breadboard and nothing more. It's just wires. There's no need to shove transistors in there.
    Reply
  • kwohlt
    jkflipflop98 said:
    Wut? Exactly what advantages do you suppose putting cache on the interposer will provide? How would you even use that? The interposer is a fancy smart breadboard and nothing more. It's just wires. There's no need to shove transistors in there.
    The advantage of 3D stacking is die space. The die doesn't have room for the rumored 128MB of L4 cache. The rumor was 3D stacked cache by placing the L4 in the active interposer, which would also allow better cooling as the compute tile would be in direct contact with the IHS, rather than being beneath the cache as X3D does.
    Reply
  • hilive
    This would be ideal for appliance-type devices for which people never upgrade the RAM anyway. Examples:
    1. Chromebooks
    2. tablets
    3. ultrabooks
    4. gaming consoles (Steam Deck competitors)

    And the idea that the integrated RAM will make heat problems significantly worse is strange. First off, this isn't going to be used on workbooks with 32 or 64 GB RAM. It is going to be used for consumer and prosumer devices like the Dell XPS 13. Even if it did, the node shrink - going from 10nm for Raptor Lake to 7nm for Meteor Lake - would more than overcompensate for it anyway.
    Reply
  • Lucky_SLS
    They could have gone with 24gb Memory considering that igpu would use from the same Memory pool.

    This would be an interesting AMD Z1 extreme competitor.
    Reply
  • jkflipflop98
    kwohlt said:
    The advantage of 3D stacking is die space. The die doesn't have room for the rumored 128MB of L4 cache. The rumor was 3D stacked cache by placing the L4 in the active interposer, which would also allow better cooling as the compute tile would be in direct contact with the IHS, rather than being beneath the cache as X3D does.

    Your OP didn't say anything about die stacking. You said "where is this interposer with the cache that was rumored." Foveros doesn't need cache itself. You add cache by stacking it on top. There's no need for it to be IN the breadboard.
    Reply
  • Yeshwant Kethineni
    I would hope with on package memory you would be able to do better than 7500MT/s / 120Gbps bandwidth, but I guess not
    Reply