Anton Shilov

Margins or openness? Margins!

Massive AI clusters cost massively.

Malaysia’s trade ministry is investigating whether a Chinese firm’s use of Nvidia-equipped servers in a local data center violates domestic laws.

New design could inform CFET transistor production.

But the prices are still unknown...

Coming in 2026?

Intel's upcoming Core Ultra 9 'Nova Lake-S' desktop CPUs will reportedly feature up to 52 cores, DDR5-8000 memory support, and 32 PCIe 5.0 lanes. What a beast!

Other divisions will face similar reductions.

It is going to get hot.

KAIST has a roadmap projecting the evolution of high-bandwidth memory from HBM4 to HBM8 through 2038, detailing major gains in bandwidth, capacity, I/O width, power, and even system architecture.

Huawei has reportedly developed a chip packaging process technology for its Ascend 910D processor that is comparable to TSMC's leading-edge CoWoS technology.

Client PC PCIe 6.0 x4 SSDs offering up to 32 GB/s bandwidth are not arriving until around 2030 due to high implementation costs, according to Silicon Motion CEO.

The chief executive of Silicon Motion said in an interview that Nvidia is looking forward to ridiculously fast storage devices to eliminate performance bottlenecks for its AI GPUs.

Intel will begin layoffs at its Intel Foundry division in mid-July as part of a new restructuring effort to cut costs while focusing on keeping engineering talent.

Contemporary AI models are not silly, Apple just does not have proper hardware to test their limitations, says professor Seokjun Kwon of Sungkyunkwan University.

Oracle Cloud Infrastructure will be the first major cloud provider to deploy AMD's Instinct MI350X GPUs and Pensando Pollara 400GbE Ultra Ethernet NICs as part of a massive zettascale AI cluster.

AMD's software stack for AI keeps improving.

Will at least double performance compared to existing MI355X-based solutions.

AMD plans to launch its second-generation rack-scale AI platform in 2027 with EPYC 'Verano' CPUs, Instinct MI500X GPUs, and Vulcano 800 GbE NICs, accelerating its roadmap to an annual cadence.

AMD’s Zen 6-based EPYC ‘Venice’ CPU pushes core count to 256, boosts performance by 70%, and features PCIe 6.0, 1.6 TB/s memory bandwidth, and a new SP7 packaging, according to AMD.

Micron has become the first DRAM vendor to begin sampling 36GB HBM4 memory with a 2048-bit interface and 2TB/s bandwidth.

PCI-SIG has revealed the specs for PCIe 7.0, and its plans for 8.0.

A lot of questions, a lot of answers.

As power consumption of accelerators for supercomputers continues to grow in the coming years, AMD expects zetta scale-class datacenters to consume 500 megawatts, require nuclear reactor.

An expensive delay