Deep Analysis
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PremiumIntel patent embeds MicroLEDs in chip packaging — technology may enable embedded optical interconnects through TGVsThis follows over a decade of Intel investment in glass substrate technology.
By Jon Martindale Published -
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PremiumSynopsys debuts Autopilot platform for developing chips autonomously using AISynopsys unveiled seven AgentEngineer agents on its new Autopilot platform, with general availability planned for the end of 2026.
By Shane Downing Published -
PremiumTower Semiconductor to invest $4 billion in Japanese ops to set up massive optical connectivity hubTower's new optical connectivity hub in Japan will increase its output by 40 times in 2029 compared to 2025 level.
By Anton Shilov Published
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PremiumHot Chips 2026: Micron warns HBM wafer penalty is widening with every generationMicron Fellow Raghu Sreeramaneni told the Hot Chips 2026 conference that the silicon penalty HBM carries against DDR5 is growing with every generation.
By Luke James Published -
PremiumHot Chips 2026: Nvidia breaks down 88-core Vera CPUNvidia has provided more color on its Vera CPU for agentic data centers at Hot Chips 2026, showcasing the benefits of spatial multithreading and the power benefits of the LPDDR5X memory system.
By Jake Roach Published -
PremiumHot Chips 2026: Intel Xeon 7 'Diamond Rapids' comes with up to 256 P-cores, 1.28 GB of last-level cacheIntel has pulled back the curtain on its next-gen Diamond Rapids Xeon CPUs, packing up to 256 P-cores and 1.28 TB of last-level cache.
By Jake Roach Published -
PremiumHot Chips 2026: SK hynix pushes hybrid bonding to HBM5 as AI memory hits 775-micron ceilingThe problem, per SK, is that HBM cubes are capped at a total thickness of 775 microns, the standard thickness of a 300mm logic wafer.
By Luke James Published -
PremiumHot Chips 2026: IBM's first dual-ISA core natively executes ARM and z/Architecture in the same core; all cores run at 5.7 GHz base frequencyIBM is vastly expanding softwarte support on its mainframes with its first dual-ISA CPU core that natively supports z/Architecture and ARM instructions.
By Jake Roach Published -
PremiumMarvell VP pushes for DDR4 recycling for use in CXL memory, amid the worst DRAM shortage in years — company introduces three-tier AI memory infrastructureMarvell has introduced a three-tier "AI memory infrastructure" portfolio, announced at FMS 2026 in Santa Clara on August 4.
By Luke James Published -
PremiumH200s finally reach China under case-by-case import licenses, but it's already too late for NvidiaMost of each company's U.S.-licensed allowance, understood to be up to 100,000 units apiece, must stay outside the mainland.
By Luke James Published -
PremiumSMIC posts record $3B quarter and hikes wafer pricesSMIC posted its first $3 billion quarter earlier this month, with revenue up 36.1% year on year, net profit nearly tripling to $479.2 million.
By Luke James Published -
PremiumAjinomoto reportedly cuts critical chip packaging film supply to China by 30% as domestic substitutes race to qualifyJapanese chemical maker Ajinomoto has reportedly told customers in mainland China that it will cut the supply of ABF.
By Luke James Published
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