The memory hierarchy of Conroe was extremely simple and Intel was able to concentrate on the performance of the shared L2 cache, which was the best solution for an architecture that was aimed mostly at dual-core implementations. But with Nehalem, the engineers started from scratch and came to the same conclusions as their competitors: a shared L2 cache was not suited to a native quad-core architecture. The different cores can too frequently flush data needed by another core and that surely would have involved too many problems in terms of internal buses and arbitration to provide all four cores with sufficient bandwidth while keeping latency sufficiently low. To solve the problem, the engineers provided each core with a Level 2 cache of its own. Since it’s dedicated to a single core and relatively small (256 KB), the engineers were able to endow it with very high performance; latency, in particular, has reportedly improved significantly over Penryn—from 15 cycles to approximately 10 cycles.
Then comes an enormous Level 3 cache memory (8 MB) for managing communications between cores. While at first glance Nehalem’s cache hierarchy reminds one of Barcelona, the operation of the Level 3 cache is very different from AMD’s—it’s inclusive of all lower levels of the cache hierarchy. That means that if a core tries to access a data item and it’s not present in the Level 3 cache, there’s no need to look in the other cores’ private caches—the data item won’t be there either. Conversely, if the data are present, four bits associated with each line of the cache memory (one bit per core) show whether or not the data are potentially present (potentially, but not with certainty) in the lower-level cache of another core, and which one.
This technique is effective for ensuring the coherency of the private caches because it limits the need for exchanges between cores. It has the disadvantage of wasting part of the cache memory with data that is already in other cache levels. That’s somewhat mitigated, however, by the fact that the L1 and L2 caches are relatively small compared to the L3 cache—all the data in the L1 and L2 caches takes up a maximum of 1.25 MB out of the 8 MB available. As on Barcelona, the Level 3 cache doesn’t operate at the same frequency as the rest of the chip. Consequently, latency of access to this level is variable, but it should be in the neighborhood of 40 cycles.
The only real disappointment with Nehalem’s new cache hierarchy is its L1 cache. The bandwidth of the instruction cache hasn’t been increased—it’s still 16 bytes per cycle compared to 32 on Barcelona. This could create a bottleneck in a server-oriented architecture since 64-bit instructions are larger than 32-bit ones, especially since Nehalem has one more decoder than Barcelona, which puts that much more pressure on the cache. As for the data cache, its latency has increased to four cycles compared to three on the Conroe, facilitating higher clock frequencies. To end on a positive note, though, the engineers at Intel have increased the number of Level 1 data cache misses that the architecture can process in parallel.


I regard being late as a quality seal really. No point being first, if your info is only as credible as stuff on inquirer. Better be last, but be sure what you write is correct.
Perhaps, if you count being translated from French.
Nice article, good depth, well written
I don't know french, so no idea if it actually works. But I've tried from english to germany and danish, and viseversa. Also tried from danish to german, and the result is always the same - it's incomplete, and anything that is slighty technical in nature won't be translated properly. In short - want it done right, do it yourself.
You claimed the article on toms was a copy paste from another article. He merely stated that the article here was based on a french version.
I actually read the whole thing.
I just don't get TLP when RAM is cheap and the Nehalem/Vista can address 128gigs. Anyway, things have changed a lot since running Win NT with 16megs RAM and constant memory swapping.
1) How's the loop detection feature know when it is a loop ? The diagrams posted don't show any connection between it and the 'front' of the pipeline, so how can it know that the next operation is the same if it hasn't yet entered the loop?
2) On page 8 there's a diagram with a 4 socket setup showing 2 io hubs. Are they connected to the same pcie bus and whatever else they interface with? or are only 2 of the sockets able to directly access a given resource?
3) With the modular design, would one risk buying a cpu that doesn't work in a motherboard because it is intended for a 2 or 4 socket system? or are they all the same, simply with some qpi's disabled?
4) Am I right assuming that qpi replaces fsb when it has to communicate with an i/o hub only? (as shown in one of the top diagrams on page 8) Or is it used for every one of the 'blue' lines on the lower diagram (10 total in a 4 socket layout). The latter would mean 4 qpi's are barely enough to satisfy bandwidth needs in a server enviroment. I imagine an esx server with 4 processors (32 threads) can easily demand memory from dram pools not linked to the local core the threads are running on, and use 96GB/s (3x32) of the 102GB/s (4x12,8x2) total theoretical bandwidth in addition to some of the local 32GB/s bandwidth from the socket a given core/thread is running on. So if this scenario is correct, is it possible to increase the speed of the qpi (read: oc the link) to increase available bandwidth? And what happends if one would successfully find ddr3-1600 modules that would run within the 1,65v limitation? Wouldn't that mean the qpi was already at its limit? (38,4GB/s per dram pool x 3 sockets not local to the core that runs a thread). I know memory isn't truely the bottleneck in modern computers, but I still find it wierd that they put so much effort into the memory controller if it isn't actually the problem. Simply adding a few qpi links between the sockets and the chipset would've solved the bandwidth issue without limiting usable memory types by choosing a certain cpu. Sure it wouldn't have improved latencies, but honestly, who cares? neither in a gaming pc, netbook or any number of common server configurations is it the memory lantecy that is the bottleneck.
5) How much time should one assume is wasted when a core on conroe flushes the l2 cache? they seem to have solved the issue and as consequence increased cache latency (which should turn into slower overall cache performance). In english : can we expect any gain from this change?
6) Would the immensely increased tlb size improve performance in newer games which precache loads of data? (thinking quicker retrieval of texture data etc)
7) Page 12 mentions unalligned memory access, which I've never heard of before. Appearently compilers already try to avoid this situation, so can we expect the improvement to handling such to be of interest? What's the point of improving a feature to handle a situation that hardly ever arises in the first place?
http://www.xbitlabs.com/articles/cpu/display/replay.html
This was a very good article and is not a copy ... well done Fedy !!
perhaps it will burn out the IMC within the chip since its all done at 45nm, 1.6+v would be deadly, imagine air cooling a 3ghz quad core chip at ~2v? i take it it shares the rail even within the cpu so
depends on how connected that ram is, there might be advantages etc this way, and it also makes you wonder if AMD suffers from this - iv heard of extreme overclockers killing ram channels on AMD's etc
on the other hand who cares about high performance memory - 3 x 1333mhz is going to be better then 2 x 1600+mhz channels etc, along with the fact its an IMC based setup etc and average maximum bandwidths of ~32gb/s vs the current average maximum of ~12.8gb/s etc
as for the memory issue. Who'd want to run 3x1333 if they could run 6x1600 ? any enthusiast will only be satisfied with the best, and 1333 just isn't it. Not even 1600 is. ddr3-1333 is basicly obsolete, and it's not even mainstream yet. It's a disaster really.
A case of perhaps minimising reflected impedence?
Just my theory anyway ... remember ... I am only here for the humour ... not the technology.
AMD4LIFE