New Processors: P4 Prescott Up To 3.6 GHz
Intel introduces a full line of LGA 775 processors, starting with the new Celeron D at 2.53 to 2.80 GHz. Although these low-cost chips are finally based on the 90 nm process, it does not make them really attractive. They lack HyperThreading and all the features that are actually responsible for turning the current Intel architecture into a family of rapid workers: a decent cache size, a fast system bus speed (called Front Side Bus or FSB) and high clock speeds. While the FSB speed now is 133 MHz in quad data rate mode (FSB 533), the L2 cache size remains limited to 256 kB. In exchange, Celerons are cheap.
Apparently the pins have gone.
Next, a few words on HyperThreading as a refresher - Windows will detect and run two virtual processors on a HT-enabled computer. Intel has tried to increase the utilization of the processor's execution resources, as it is not always possible to efficiently feed the execution units with suitable instructions. For this reason, a feature called out-of-order execution helps to rearrange instructions, but a thread-based approach seemed to be the better solution. Thread-based software benefits from multi-processing computers because they are able to share the thread load to all processors available. What Intel has introduced with HyperThreading is the ability of a single processor to process multiple threads simultaneously.
In this respect, the new Pentium 4 processors are much more interesting, as they run FSB 800, come with 1 MB L2 cache and master HyperThreading. From now on, all future Intel processors will be identified by their processor number rather than by pure clock speed. The reason for this is that Intel is finally hitting the clock speed ceiling - ratcheting up the clock speed is becoming more and more difficult and, at the same time, today's rather small increases 200 MHz don't pay off much with regard to performance.
The 3.4 and 3.6 GHz versions are the most controversial chips, as they will likely be available in homeopathic quantities now - if they will be available at all. This is very likely going to be almost a paper launch until the E0 stepping introduces active power control to the processor line to dam the power loss. After having seen the temperature levels of a 3.6 GHz system, that strategy wouldn't surprise me.
